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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [RLI_coding_logic.vhd] - Blame information for rev 9

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1 8 eejlny
--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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---------------------------------------------
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--  ENTITY       =  RLI_coding_logic       --
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--  Version      =  1.0                    --
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--  last update  =  22/11/99               --
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--  author       =  Jose Nunez             --
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---------------------------------------------
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-- FUNCTION
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-- RLI logic for the compression process
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--  PIN LIST
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--  RL_DETECTED : run length detection
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--  COUNT_IN : count coming from the share counter
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--  COMP_IN : control signal from csm
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--  FLUSH_IN : control signal from csm
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--  CODE_IN :normal code in
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--  LENGTH_IN : length of code in
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--  CLEAR : asyncronous clear
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--  CLK : master clock
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--  FLUSH_OUT : control signal from csm
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--  COMP_OUT : control signal from csm
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--  CODE_OUT : 33 bits code out
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--  LENGTH_OUT : length of code out
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library ieee;
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use ieee.std_logic_1164.all;
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entity RLI_coding_logic is
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port
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(
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          RL_DETECTED : in bit;
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          COUNT_IN : in bit_vector(7 downto 0);
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          COMP_IN : in bit;
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          MOVE_ENABLE_IN : in bit;
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          FLUSH_IN: in bit;
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    FLUSH_RLI : in bit;
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          CODE_IN : in bit_vector(34 downto 0);
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          LENGTH_IN : in bit_vector(5 downto 0);
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          CODE_RLI : in bit_vector(4 downto 0);
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      CODE_RLI_LENGTH : in bit_vector(2 downto 0);
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          CLEAR : in bit;
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          RESET : in bit;
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          CLK : in bit;
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          FLUSH_OUT: out bit;
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          COMP_OUT: out bit;
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          CODE_OUT : out bit_vector(34 downto 0);
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          LENGTH_OUT : out bit_vector(5 downto 0)
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);
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end RLI_coding_logic;
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architecture STRUCTURAL of RLI_coding_logic is
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component RLI_CCU
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port
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(
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      CODE_IN : in bit_vector(34 downto 0) ;
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          MOVE_ENABLE_IN: in bit;
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          FLUSH_IN : in bit;
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          LENGTH_IN : in bit_vector (5 downto 0);
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          CODE_RLI : in bit_vector(4 downto 0);
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          CODE_RLI_LENGTH : in bit_vector(2 downto 0);
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          COUNT : in bit_vector(7 downto 0);
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          RL_DETECTED : in bit;
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      CLEAR : in bit ;
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          RESET : in bit;
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      CLK : in bit ;
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      CODE_OUT : out bit_vector(34 downto 0);
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          LENGTH_OUT : out bit_vector(5 downto 0)
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);
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end component;
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component RLI_CR
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port         (
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                        FLUSH_IN : in bit;
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                        CODE_IN : in bit_vector (34 downto 0);
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                        LENGTH_IN : in bit_vector (5 downto 0);
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                        CODE_RLI_IN : in bit_vector(4 downto 0);
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                        CODE_RLI_LENGTH_IN : in bit_vector(2  downto 0);
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                        COMP_IN :in bit;
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                        MOVE_ENABLE_IN: in bit;
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                        CLEAR:in bit;
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                        RESET: in bit;
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                        CLK :in bit;
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                        FLUSH_OUT:out bit;
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                        CODE_OUT:out bit_vector(34 downto 0);
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                        LENGTH_OUT:out bit_vector(5 downto 0);
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                        CODE_RLI_OUT : out bit_vector(4 downto 0);
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                        CODE_RLI_LENGTH_OUT : out bit_vector(2 downto 0);
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                        COMP_OUT: out bit;
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                        MOVE_ENABLE_OUT : out bit
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                );
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end component;
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signal LENGTH_OUT_INT : bit_vector(5 downto 0); -- length to the control unit
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signal CODE_OUT_INT : bit_vector(34 downto 0); -- code to the control unit
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signal CODE_RLI_OUT_INT : bit_vector(4 downto 0);
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signal CODE_RLI_LENGTH_OUT_INT : bit_vector(2  downto 0);
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signal MOVE_ENABLE_OUT: bit;
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signal FLUSH_OUT_INT: bit;
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begin
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coding_register : RLI_CR
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port map(
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                        FLUSH_IN => FLUSH_IN,
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                        CODE_IN => CODE_IN,
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                        LENGTH_IN => LENGTH_IN,
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                        CODE_RLI_IN => CODE_RLI,
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                        CODE_RLI_LENGTH_IN => CODE_RLI_LENGTH,
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                        COMP_IN => COMP_IN,
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                        MOVE_ENABLE_IN => MOVE_ENABLE_IN,
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                        CLEAR => CLEAR,
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                        RESET => RESET,
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                        CLK => CLK,
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                        FLUSH_OUT => FLUSH_OUT_INT,
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                        CODE_OUT => CODE_OUT_INT,
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                        LENGTH_OUT => LENGTH_OUT_INT,
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                        CODE_RLI_OUT => CODE_RLI_OUT_INT,
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                        CODE_RLI_LENGTH_OUT => CODE_RLI_LENGTH_OUT_INT,
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                        COMP_OUT => COMP_OUT,
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                        MOVE_ENABLE_OUT => MOVE_ENABLE_OUT
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                );
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control_unit : RLI_CCU
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port map
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(
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      CODE_IN => CODE_OUT_INT,
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          MOVE_ENABLE_IN => MOVE_ENABLE_IN,
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          FLUSH_IN => FLUSH_RLI,
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          LENGTH_IN => LENGTH_OUT_INT,
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      CODE_RLI => CODE_RLI_OUT_INT,
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          CODE_RLI_LENGTH => CODE_RLI_LENGTH_OUT_INT,
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          COUNT => COUNT_IN,
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          RL_DETECTED => RL_DETECTED,
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      CLEAR => CLEAR,
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          RESET => RESET,
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      CLK => CLK,
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      CODE_OUT => CODE_OUT,
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          LENGTH_OUT => LENGTH_OUT
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);
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FLUSH_OUT <= FLUSH_OUT_INT;
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end STRUCTURAL;
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