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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [latch98.vhd] - Blame information for rev 9

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1 8 eejlny
--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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---------------------------------
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--  ENTITY       = LATCH98     --
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--  version      = 1.0         --
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--  last update  = 1/06/01    --
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--  author       = Jose Nunez  --
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---------------------------------
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-- FUNCTION
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-- 99 bit latch
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-- PIN LIST
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-- D_IN  = input data bus
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-- CLEAR = asynchronous clear of latch
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-- CLK   = master clock
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-- D_OUT = output data bus
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library ieee,dzx;
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use ieee.std_logic_1164.all;
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entity LATCH98 is
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port
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(
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        D_IN : in bit_vector(97 downto 0);
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        CLEAR : in bit;
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        RESET : in bit;
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        CLK : in bit;
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        D_OUT : out bit_vector(97 downto 0)
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);
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end LATCH98;
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architecture FLIP_FLOP of LATCH98 is
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begin
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FLOP : process (CLK,CLEAR)
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begin
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if (CLEAR = '0') then
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    D_OUT <= "00" & x"000000000000000000000000";
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elsif ((CLK'event) and (CLK = '1')) then
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        if (RESET = '0') then
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        D_OUT <= "00" & x"000000000000000000000000";
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    else
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                D_OUT <= D_IN;
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    end if;
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end if;
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end process FLOP;
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end FLIP_FLOP; -- end of architecture
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