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--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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-- Name = mem1
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-- type = RAM
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-- width = 32
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-- depth = 256
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-- part family = A500K
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-- output type = transparent
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-- optimization = speed
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-- input type = synchronous
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-- parity control = ignore
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-- Write = active high
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-- Read = active high
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-- Read clock = posedge
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-- Write clock = posedge
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library IEEE;
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use IEEE.std_logic_1164.all;
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library A500K;
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use A500K.all;
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entity MY_MEMORY is
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port(DO : out std_logic_vector (31 downto 0);
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RCLOCK : in std_logic;
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WCLOCK : in std_logic;
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DI : in std_logic_vector (31 downto 0);
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WRB : in std_logic;
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RDB : in std_logic;
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WADDR : in std_logic_vector (7 downto 0);
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RADDR : in std_logic_vector (7 downto 0));
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end MY_MEMORY;
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architecture STRUCT of MY_MEMORY is
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component PWR
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port(Y : out std_logic);
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end component;
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attribute black_box: boolean;
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attribute black_box of PWR: component is true;
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component GND
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port(Y : out std_logic);
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end component;
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-- attribute black_box: boolean;
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attribute black_box of GND: component is true;
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component RAM256x9SST
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port(RCLKS : in std_logic;
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WCLKS : in std_logic;
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DO8 : out std_logic;
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DO7 : out std_logic;
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DO6 : out std_logic;
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DO5 : out std_logic;
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DO4 : out std_logic;
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DO3 : out std_logic;
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DO2 : out std_logic;
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DO1 : out std_logic;
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DO0 : out std_logic;
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DOS : out std_logic;
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WPE : out std_logic;
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RPE : out std_logic;
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WADDR7 : in std_logic;
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WADDR6 : in std_logic;
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WADDR5 : in std_logic;
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WADDR4 : in std_logic;
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WADDR3 : in std_logic;
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WADDR2 : in std_logic;
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WADDR1 : in std_logic;
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WADDR0 : in std_logic;
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RADDR7 : in std_logic;
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RADDR6 : in std_logic;
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RADDR5 : in std_logic;
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RADDR4 : in std_logic;
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RADDR3 : in std_logic;
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RADDR2 : in std_logic;
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RADDR1 : in std_logic;
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RADDR0 : in std_logic;
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DI8 : in std_logic;
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DI7 : in std_logic;
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DI6 : in std_logic;
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DI5 : in std_logic;
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DI4 : in std_logic;
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DI3 : in std_logic;
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DI2 : in std_logic;
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DI1 : in std_logic;
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DI0 : in std_logic;
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WRB : in std_logic;
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RDB : in std_logic;
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WBLKB : in std_logic;
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RBLKB : in std_logic;
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PARODD : in std_logic;
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DIS : in std_logic);
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end component;
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-- attribute black_box: boolean;
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attribute black_box of RAM256x9SST: component is true;
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component INV
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port(Y : out std_logic;
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A : in std_logic);
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end component;
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-- attribute black_box: boolean;
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attribute black_box of INV: component is true;
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signal WADDRAUX : std_logic_vector(7 downto 0); -- artificial delays
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signal RADDRAUX : std_logic_vector(7 downto 0);
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signal WRBAUX : std_logic;
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signal RDBAUX : std_logic;
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signal DIAUX : std_logic_vector(31 downto 0);
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signal VDD, VSS, n1, n2 : std_logic;
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begin
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WADDRAUX <= WADDR after 5 ns;
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RADDRAUX <= RADDR after 5 ns;
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WRBAUX <= WRB after 5 ns;
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RDBAUX <= RDB after 5 ns;
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DIAUX <= DI after 5 ns;
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U1 : GND port map(Y => VSS);
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M0 : RAM256x9SST port map(RCLKS =>RCLOCK, WCLKS => WCLOCK, DO8 => DO(8), DO7 => DO(7), DO6 => DO(6),
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DO5 => DO(5), DO4 => DO(4), DO3 => DO(3), DO2 => DO(2), DO1 => DO(1),
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DO0 => DO(0), WADDR7 => WADDRAUX(7), WADDR6 => WADDRAUX(6), WADDR5 => WADDRAUX(5),
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WADDR4 => WADDRAUX(4), WADDR3 => WADDRAUX(3), WADDR2 => WADDRAUX(2), WADDR1 => WADDRAUX(1),
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WADDR0 => WADDRAUX(0), RADDR7 => RADDRAUX(7), RADDR6 => RADDRAUX(6), RADDR5 => RADDRAUX(5),
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RADDR4 => RADDRAUX(4), RADDR3 => RADDRAUX(3), RADDR2 => RADDRAUX(2), RADDR1 => RADDRAUX(1),
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RADDR0 => RADDRAUX(0), DI8 => DIAUX(8), DI7 => DIAUX(7), DI6 => DIAUX(6), DI5 => DIAUX(5),
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DI4 => DIAUX(4), DI3 => DIAUX(3), DI2 => DIAUX(2), DI1 => DIAUX(1), DI0 => DIAUX(0),
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WRB => n1, RDB => n2, WBLKB => VSS, RBLKB => VSS, PARODD => VSS, DIS => VSS);
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M1 : RAM256x9SST port map(RCLKS =>RCLOCK, WCLKS => WCLOCK, DO8 => DO(17), DO7 => DO(16), DO6 => DO(15),
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DO5 => DO(14), DO4 => DO(13), DO3 => DO(12), DO2 => DO(11), DO1 => DO(10),
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DO0 => DO(9), WADDR7 => WADDRAUX(7), WADDR6 => WADDRAUX(6), WADDR5 => WADDRAUX(5),
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WADDR4 => WADDRAUX(4), WADDR3 => WADDRAUX(3), WADDR2 => WADDRAUX(2), WADDR1 => WADDRAUX(1),
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WADDR0 => WADDRAUX(0), RADDR7 => RADDRAUX(7), RADDR6 => RADDRAUX(6), RADDR5 => RADDRAUX(5),
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RADDR4 => RADDRAUX(4), RADDR3 => RADDRAUX(3), RADDR2 => RADDRAUX(2), RADDR1 => RADDRAUX(1),
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RADDR0 => RADDRAUX(0), DI8 => DIAUX(17), DI7 => DIAUX(16), DI6 => DIAUX(15), DI5 => DIAUX(14),
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DI4 => DIAUX(13), DI3 => DIAUX(12), DI2 => DIAUX(11), DI1 => DIAUX(10), DI0 => DIAUX(9),
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WRB => n1, RDB => n2, WBLKB => VSS, RBLKB => VSS, PARODD => VSS, DIS => VSS);
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M2 : RAM256x9SST port map(RCLKS =>RCLOCK, WCLKS => WCLOCK, DO8 => DO(26), DO7 => DO(25), DO6 => DO(24),
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DO5 => DO(23), DO4 => DO(22), DO3 => DO(21), DO2 => DO(20), DO1 => DO(19),
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DO0 => DO(18), WADDR7 => WADDRAUX(7), WADDR6 => WADDRAUX(6), WADDR5 => WADDRAUX(5),
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WADDR4 => WADDRAUX(4), WADDR3 => WADDRAUX(3), WADDR2 => WADDRAUX(2), WADDR1 => WADDRAUX(1),
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WADDR0 => WADDRAUX(0), RADDR7 => RADDRAUX(7), RADDR6 => RADDRAUX(6), RADDR5 => RADDRAUX(5),
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RADDR4 => RADDRAUX(4), RADDR3 => RADDRAUX(3), RADDR2 => RADDRAUX(2), RADDR1 => RADDRAUX(1),
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RADDR0 => RADDRAUX(0), DI8 => DIAUX(26), DI7 => DIAUX(25), DI6 => DIAUX(24), DI5 => DIAUX(23),
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DI4 => DIAUX(22), DI3 => DIAUX(21), DI2 => DIAUX(20), DI1 => DIAUX(19), DI0 => DIAUX(18),
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WRB => n1, RDB => n2, WBLKB => VSS, RBLKB => VSS, PARODD => VSS, DIS => VSS);
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M3 : RAM256x9SST port map(RCLKS =>RCLOCK, WCLKS => WCLOCK, DO4 => DO(31), DO3 => DO(30), DO2 => DO(29),
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DO1 => DO(28), DO0 => DO(27), WADDR7 => WADDRAUX(7), WADDR6 => WADDRAUX(6), WADDR5 => WADDRAUX(5),
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WADDR4 => WADDRAUX(4), WADDR3 => WADDRAUX(3), WADDR2 => WADDRAUX(2), WADDR1 => WADDRAUX(1),
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WADDR0 => WADDRAUX(0), RADDR7 => RADDRAUX(7), RADDR6 => RADDRAUX(6), RADDR5 => RADDRAUX(5),
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RADDR4 => RADDRAUX(4), RADDR3 => RADDRAUX(3), RADDR2 => RADDRAUX(2), RADDR1 => RADDRAUX(1),
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RADDR0 => RADDRAUX(0), DI8 => VSS, DI7 => VSS, DI6 => VSS, DI5 => VSS, DI4 => DIAUX(31), DI3 => DIAUX(30),
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DI2 => DIAUX(29), DI1 => DIAUX(28), DI0 => DIAUX(27), WRB => n1, RDB => n2, WBLKB => VSS, RBLKB => VSS,
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PARODD => VSS, DIS => VSS);
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U2 : INV port map(Y => n1, A => WRBAUX);
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U3 : INV port map(Y => n2, A => RDBAUX);
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end STRUCT;
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