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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [src/] [output_buffer_32_32.vhd] - Blame information for rev 9

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1 8 eejlny
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--  ENTITY       = OUTPUT_BUFFER_32_32     --
4
 
5
--  version      = 1.0                     --
6
 
7
--  last update  = 30/05/01                --
8
 
9
--  author       = Jose Nunez              --
10
 
11
--  Modified:    Vassilios A. Chouliaras 270204
12
 
13
--               Added TSMC013 DPRAM with
14
 
15
--               minor mods to strobe generation
16
 
17
---------------------------------------------
18
 
19
 
20
 
21
 
22
 
23
-- FUNCTION
24
 
25
-- This output buffer loads 32 bits of data from the decompression engine and writes 32 bit of data to the output bus
26
 
27
-- 256x32 bit word to handle a block of 1 Kbyte. Then the buffer waits for the all data processed signal before requesting more data.
28
 
29
 
30
 
31
--  PIN LIST
32
 
33
 
34
 
35
--  START = activate the buffer
36
 
37
--  WRITE = write data from the engine to the buffer
38
 
39
--  FINISHED = all the data has accessed the buffer. Engine has finished
40
 
41
--  DATA_IN_32  = input data from the 32 bit decompression engine
42
 
43
--  THRESHOLD = data that must be present in the buffer when data starts being output
44
 
45
--  BUS_ACKNOWLEDGE = starting outputting data to the output bus
46
 
47
--  DATA_OUT_32  = output data to the 32 bit wide output bus
48
 
49
--  READY = data ready in the buffer
50
 
51
--  BUS_REQUEST = output requesting bus to start outputting databe processed
52
 
53
--  CLEAR    = asynchronous clear
54
 
55
--  CLK      = master clock
56
 
57
 
58
 
59
 
60
 
61
library ieee,dzx;
62
 
63
use ieee.std_logic_1164.all;
64
 
65
use IEEE.std_logic_arith.all;
66
 
67
use dzx.bit_arith.all;
68
 
69
library xil_lib;
70
use xil_lib.xil_comp.all;
71
use work.tech_package.all;
72
 
73
 
74
 
75
 
76
 
77
entity OUTPUT_BUFFER_32_32 is
78
 
79
port
80
 
81
(
82
 
83
        FORCE_STOP : in bit;
84
 
85
        START_D : in bit;
86
 
87
        START_C : in bit;
88
 
89
        WRITE : in bit;
90
 
91
        FINISHED : in bit;
92
 
93
  WAITN : in bit; -- introduce wait cycles
94
 
95
        DATA_IN_32 : in bit_vector(31 downto 0);
96
 
97
        THRESHOLD : in bit_vector(7 downto 0);
98
 
99
        BUS_ACKNOWLEDGE : in bit;
100
 
101
        CLEAR : in bit ;
102
 
103
        CLK : in bit ;
104
 
105
        FLUSHING : out bit;
106
 
107
        FINISHED_FLUSHING : out bit;
108
 
109
        OVERFLOW_DETECTED : out bit;
110
 
111
        DATA_OUT_32: out bit_vector(31 downto 0);
112
 
113
        READY : out bit;
114
 
115
  OVERFLOW_CONTROL : out bit;
116
 
117
        BUS_REQUEST : out bit
118
 
119
);
120
 
121
 
122
 
123
end OUTPUT_BUFFER_32_32;
124
 
125
 
126
 
127
 
128
 
129
architecture STRUCTURAL of OUTPUT_BUFFER_32_32 is
130
 
131
 
132
 
133
-- xilinx memory
134
 
135
 
136
 
137
component DP_RAM_XILINX_512
138
 
139
        port (
140
 
141
        addra: IN std_logic_VECTOR(8 downto 0);
142
 
143
        clka: IN std_logic;
144
 
145
        addrb: IN std_logic_VECTOR(8 downto 0);
146
 
147
        clkb: IN std_logic;
148
 
149
        dina: IN std_logic_VECTOR(31 downto 0);
150
 
151
        wea: IN std_logic;
152
 
153
        enb: IN std_logic;
154
 
155
        doutb: OUT std_logic_VECTOR(31 downto 0));
156
 
157
end component;
158
 
159
 
160
 
161
-- Synplicity black box declaration
162
 
163
--attribute black_box : boolean;
164
 
165
--attribute black_box of DP_RAM_XILINX: component is true;
166
 
167
 
168
 
169
 
170
 
171
-- Actel memory
172
 
173
 
174
 
175
-- component MY_MEMORY
176
 
177
 
178
 
179
--   port(DO : out std_logic_vector (31 downto 0);
180
 
181
--      RCLOCK : in std_logic;
182
 
183
--      WCLOCK : in std_logic;
184
 
185
--      DI : in std_logic_vector (31 downto 0);
186
 
187
--      WRB : in std_logic;
188
 
189
--      RDB : in std_logic;
190
 
191
--      WADDR :   in std_logic_vector (7 downto 0);
192
 
193
--      RADDR : in std_logic_vector (7 downto 0)
194
 
195
--        );
196
 
197
 
198
 
199
-- end component;
200
 
201
 
202
 
203
 
204
 
205
 
206
 
207
--component syn_dpram_256x32_rawr
208
 
209
--port (
210
 
211
--              Data : in std_logic_vector(31 downto 0);
212
 
213
--              RdAddress : in std_logic_vector(7 downto 0);
214
 
215
--              WrAddress : in std_logic_vector(7 downto 0);
216
 
217
--              RdEn : in std_logic;
218
 
219
--              WrEn : in std_logic;
220
 
221
--              Q : out std_logic_vector(31 downto 0);
222
 
223
--              RdClock : in std_logic;
224
 
225
--              RdClken : in std_logic;
226
 
227
--              WrClock : in std_logic;
228
 
229
--              WrClken : in std_logic
230
 
231
--           );
232
 
233
--end component;
234
 
235
 
236
 
237
--component LPM_RAM_DP
238
--
239
--      generic (LPM_WIDTH    : positive ;
240
--
241
--               LPM_WIDTHAD  : positive;
242
--
243
--               LPM_NUMWORDS : positive;
244
--
245
--               LPM_INDATA   : string;
246
--
247
--               LPM_RDADDRESS_CONTROL : string;
248
--
249
--               LPM_WRADDRESS_CONTROL : string;
250
--
251
--               LPM_OUTDATA  : string;
252
--
253
--              LPM_TYPE     : string;
254
--
255
--               LPM_FILE     : string;
256
--
257
---------------------------------------------------------------------------------
258
--
259
--               LPM_HINT           : string);
260
--
261
--      port (RDCLOCK : in std_logic;
262
--
263
--            RDCLKEN : in std_logic;
264
--
265
--            RDADDRESS : in std_logic_vector(8 downto 0);
266
--
267
--           RDEN : in std_logic;
268
--
269
--            DATA : in std_logic_vector(31 downto 0);
270
--
271
--           WRADDRESS : in std_logic_vector(8 downto 0);
272
--
273
--            WREN : in std_logic;
274
--
275
--            WRCLOCK : in std_logic;
276
--
277
--            WRCLKEN : in std_logic;
278
--
279
--            Q : out std_logic_vector(31 downto 0));
280
--
281
--end component;
282
 
283
 
284
 
285
--attribute noopt: boolean;
286
 
287
--attribute noopt of LPM_RAM_DP: component is true;
288
 
289
-- TSMC DPRAM
290
 
291
  component ra2sh_512W_32B_16MX_offWRMSK_8WRGRAN
292
 
293
 
294
 
295
  port (
296
 
297
        CLKA: in std_logic;
298
 
299
        CENA: in std_logic;
300
 
301
        WENA: in std_logic;
302
 
303
        AA: in std_logic_vector(8 downto 0);
304
 
305
        DA: in std_logic_vector(31 downto 0);
306
 
307
        QA: out std_logic_vector(31 downto 0);
308
 
309
        CLKB: in std_logic;
310
 
311
        CENB: in std_logic;
312
 
313
        WENB: in std_logic;
314
 
315
        AB: in std_logic_vector(8 downto 0);
316
 
317
        DB: in std_logic_vector(31 downto 0);
318
 
319
        QB: out std_logic_vector(31 downto 0)
320
 
321
    );
322
 
323
    end component;
324
 
325
 
326
 
327
component OUTPUT_BUFFER_CU
328
 
329
 
330
 
331
port (
332
 
333
                WAITN : in bit;
334
 
335
                FORCE_STOP : in bit;
336
 
337
          START_D : in bit;
338
 
339
          START_C : in bit;
340
 
341
          FINISHED  : in bit;
342
 
343
          BUS_ACKNOWLEDGE : in bit;
344
 
345
          CODING_READ_ADDRESS : in bit_vector(8 downto 0);
346
 
347
          CODING_WRITE_ADDRESS : in bit_vector(8 downto 0);
348
 
349
          FLUSHING : out bit;
350
 
351
          FINISHED_FLUSHING : out bit;
352
 
353
          OVERFLOW_DETECTED : out bit;
354
 
355
          THRESHOLD : in bit_vector(8 downto 0);
356
 
357
          CLK : in bit;
358
 
359
          CLEAR : in bit;
360
 
361
          ENABLE_WRITE : out bit;
362
 
363
          ENABLE_READ : out bit;
364
 
365
          READY : out bit;
366
 
367
      CLEAR_COUNTERS : out bit;
368
 
369
    OVERFLOW_CONTROL : out bit;
370
 
371
          BUS_REQUEST : out bit
372
 
373
         );
374
 
375
end component;
376
 
377
 
378
 
379
 
380
 
381
component INPUT_COUNTER_9BITS
382
 
383
 
384
 
385
port (ENABLE : in bit;
386
 
387
          CLEAR : in bit;
388
 
389
          CLEAR_COUNTERS : in bit;
390
 
391
          CLK : in bit;
392
 
393
          COUNT : out bit_vector(8 downto 0)
394
 
395
     );
396
 
397
 
398
 
399
end component;
400
 
401
 
402
 
403
 
404
 
405
-- 1 bit for the 64-to-32 multiplexor
406
 
407
 
408
 
409
signal CODING_READ_ADDRESS : bit_vector(8 downto 0);
410
 
411
signal CODING_WRITE_ADDRESS : bit_vector(8 downto 0);
412
 
413
signal ENABLE_WRITE : bit;
414
 
415
signal DATA_OUT_AUX : std_logic_vector(31 downto 0);
416
 
417
signal READ_CLK : bit;
418
 
419
signal WRITE_CLK : bit;
420
 
421
signal WRITE_CLK_ENABLE : bit;
422
 
423
signal READ_CLK_ENABLE : bit;
424
 
425
signal ENABLE_READ_INT : bit;
426
 
427
signal ENABLE_WRITE_INT : bit;
428
 
429
signal BUS_REQUEST_INT : bit;
430
 
431
signal CLEAR_COUNTERS : bit;
432
 
433
 
434
 
435
signal DATA_SB :std_logic_vector(31 downto 0);
436
 
437
signal RDADDRESS_SB :std_logic_vector(8 downto 0);
438
 
439
signal WRADDRESS_SB :std_logic_vector(8 downto 0);
440
 
441
signal RDEN_SB :std_logic;
442
 
443
signal WREN_SB :std_logic;
444
 
445
signal RDCLOCK_SB :std_logic;
446
 
447
signal RDCLKEN_SB :std_logic;
448
 
449
signal WRCLOCK_SB :std_logic;
450
 
451
signal WRCLKEN_SB :std_logic;
452
 
453
signal READY_AUX : bit;
454
 
455
signal THRESHOLD_AUX : bit_vector(8 downto 0);
456
 
457
 
458
 
459
signal LOGIC_0 : std_logic := '0';
460
 
461
signal tsmc_cena_n , tsmc_cenb_n : std_logic;
462
 
463
signal tsmc_wena_n , tsmc_wenb_n : std_logic;
464
 
465
begin
466
 
467
 
468
 
469
 
470
 
471
CONTROL_UNIT : OUTPUT_BUFFER_CU
472
 
473
port map(
474
 
475
                WAITN => WAITN,
476
 
477
                FORCE_STOP => FORCE_STOP,
478
 
479
          START_D=> START_D,
480
 
481
          START_C=> START_C,
482
 
483
          FINISHED => FINISHED,
484
 
485
          BUS_ACKNOWLEDGE => BUS_ACKNOWLEDGE,
486
 
487
          CODING_READ_ADDRESS => CODING_READ_ADDRESS,
488
 
489
          CODING_WRITE_ADDRESS => CODING_WRITE_ADDRESS,
490
 
491
          FLUSHING => FLUSHING,
492
 
493
          FINISHED_FLUSHING =>FINISHED_FLUSHING,
494
 
495
          OVERFLOW_DETECTED => OVERFLOW_DETECTED,
496
 
497
          THRESHOLD => THRESHOLD_AUX,
498
 
499
          CLK => CLK,
500
 
501
          CLEAR => CLEAR,
502
 
503
          ENABLE_WRITE => ENABLE_WRITE_INT,
504
 
505
          ENABLE_READ => ENABLE_READ_INT,
506
 
507
          READY => READY_AUX,
508
 
509
      CLEAR_COUNTERS => CLEAR_COUNTERS,
510
 
511
    OVERFLOW_CONTROL => OVERFLOW_CONTROL,
512
 
513
          BUS_REQUEST => BUS_REQUEST_INT
514
 
515
         );
516
 
517
 
518
 
519
 
520
 
521
 
522
 
523
READ_COUNTER : INPUT_COUNTER_9BITS
524
 
525
port map(ENABLE => READ_CLK_ENABLE,
526
 
527
          CLEAR => CLEAR,
528
 
529
          CLEAR_COUNTERS => CLEAR_COUNTERS,
530
 
531
          CLK => CLK,
532
 
533
          COUNT => CODING_READ_ADDRESS
534
 
535
     );
536
 
537
 
538
 
539
 
540
 
541
WRITE_COUNTER : INPUT_COUNTER_9BITS
542
 
543
port map(ENABLE => ENABLE_WRITE,
544
 
545
          CLEAR =>CLEAR,
546
 
547
         CLEAR_COUNTERS => CLEAR_COUNTERS,
548
 
549
          CLK => CLK,
550
 
551
          COUNT => CODING_WRITE_ADDRESS
552
 
553
     );
554
 
555
 
556
 
557
 
558
 
559
-- xilinx memory
560
 
561
 
562
 
563
RAM_SB: DP_RAM_XILINX_512
564
 
565
port map(
566
 
567
                        addra => WRADDRESS_SB,
568
 
569
                        clka =>  WRCLOCK_SB,
570
 
571
                        addrb => RDADDRESS_SB,
572
 
573
                        clkb => RDCLOCK_SB,
574
 
575
                        dina => DATA_SB,
576
 
577
                        wea => WREN_SB,
578
 
579
                        enb =>  RDEN_SB,
580
 
581
                        doutb =>  DATA_OUT_AUX);
582
 
583
 
584
 
585
 
586
 
587
-- Actel memory
588
 
589
 
590
 
591
--RAM_SB : MY_MEMORY
592
 
593
-- port map(DO => DATA_OUT_AUX,
594
 
595
--      RCLOCK =>RDCLOCK_SB,
596
 
597
--      WCLOCK =>WRCLOCK_SB,
598
 
599
--      DI => DATA_SB,
600
 
601
--      WRB => WREN_SB,
602
 
603
--      RDB =>RDEN_SB,
604
 
605
--      WADDR => WRADDRESS_SB,
606
 
607
--      RADDR => RDADDRESS_SB
608
 
609
--);
610
 
611
 
612
 
613
-- Altera memory
614
 
615
-- pragma translate off
616
 
617
--ALT_RAM :
618
--
619
--if (not TSMC013) generate
620
--
621
--RAM_SB : LPM_RAM_DP
622
--
623
-- generic map(LPM_WIDTH => 32,
624
--
625
--          LPM_WIDTHAD  => 9,
626
--
627
--          LPM_NUMWORDS => 512,
628
--
629
--               LPM_INDATA => "REGISTERED",
630
--
631
--            LPM_OUTDATA  =>  "UNREGISTERED",
632
--
633
--               LPM_RDADDRESS_CONTROL => "REGISTERED",
634
--
635
--               LPM_WRADDRESS_CONTROL => "REGISTERED",
636
--
637
--               LPM_FILE  => "UNUSED",
638
--
639
--               LPM_TYPE  => "LPM_RAM_DP",
640
--
641
--               LPM_HINT => "UNUSED")         
642
--
643
--port map(
644
--
645
--              DATA=> DATA_SB,
646
--
647
--              RDADDRESS=> RDADDRESS_SB,
648
--
649
--              WRADDRESS=> WRADDRESS_SB,
650
--
651
--              RDEN=> RDEN_SB,
652
--
653
--              WREN=> WREN_SB,
654
--
655
--              Q=> DATA_OUT_AUX,
656
--
657
--              RDCLOCK=> RDCLOCK_SB,
658
--
659
--              RDCLKEN=> RDCLKEN_SB,
660
--
661
--              WRCLOCK=> WRCLOCK_SB,
662
--
663
--              WRCLKEN=> WRCLKEN_SB
664
--
665
--);
666
--
667
--end generate;
668
 
669
--pragma translate on
670
 
671
-- Port 1 = R
672
 
673
-- Port 2 = R/W
674
 
675
--TSMC013_RAM :
676
--
677
--  if (TSMC013) generate
678
--
679
--    TMSC_RAM : ra2sh_512W_32B_16MX_offWRMSK_8WRGRAN port map
680
--
681
--      (
682
--
683
--        clka        =>      RDCLOCK_SB,
684
--
685
--        cena        =>      tsmc_cena_n ,
686
--
687
--        wena        =>      tsmc_wena_n,
688
--
689
--        aa          =>      RDADDRESS_SB,
690
--
691
--        da          =>      DATA_SB,
692
--
693
--        qa          =>      DATA_OUT_AUX,
694
--
695
--        clkb        =>      WRCLOCK_SB,
696
--
697
--        cenb        =>      tsmc_cenb_n,
698
--
699
--        wenb        =>      tsmc_wenb_n,
700
--
701
--        ab          =>      WRADDRESS_SB,
702
--
703
--        db          =>      DATA_SB,
704
--
705
--        qb          =>      OPEN
706
--
707
--      ) ;      
708
--
709
--  end generate;
710
 
711
 
712
 
713
DATA_SB<=To_X01Z(DATA_IN_32)  after 5 ns ;
714
 
715
RDADDRESS_SB<= To_X01Z(CODING_READ_ADDRESS)  after 5 ns ;
716
 
717
WRADDRESS_SB<= To_X01Z(CODING_WRITE_ADDRESS)  after 5 ns ;
718
 
719
RDEN_SB<= To_X01Z(ENABLE_READ_INT)  after 5 ns ;
720
 
721
WREN_SB<= To_X01Z(ENABLE_WRITE)  after 5 ns ;
722
 
723
RDCLOCK_SB<= To_X01Z(READ_CLK);
724
 
725
RDCLKEN_SB<= To_X01Z(READ_CLK_ENABLE)  after 5 ns ;
726
 
727
WRCLOCK_SB<= To_X01Z(WRITE_CLK);
728
 
729
WRCLKEN_SB<= To_X01Z(WRITE_CLK_ENABLE)  after 5 ns ;
730
 
731
 
732
 
733
tsmc_cenb_n <= not (WRCLKEN_SB);
734
 
735
tsmc_cena_n <= not (RDCLKEN_SB);
736
 
737
tsmc_wena_n <='1';
738
 
739
--    not (RDEN_SB); Always in read-mode; read-enable used to
740
 
741
--    power-up ram
742
 
743
tsmc_wenb_n <= not (WREN_SB);
744
 
745
 
746
 
747
DATA_OUT_32 <= To_bitvector(DATA_OUT_AUX);
748
 
749
WRITE_CLK <= CLK;
750
 
751
READ_CLK <= CLK;
752
 
753
ENABLE_WRITE <= WRITE and ENABLE_WRITE_INT and FINISHED;
754
 
755
WRITE_CLK_ENABLE <= ENABLE_WRITE_INT;
756
 
757
READ_CLK_ENABLE <= ENABLE_READ_INT and WAITN;
758
 
759
BUS_REQUEST <= BUS_REQUEST_INT;
760
 
761
READY <= READY_AUX or not(WAITN); -- no ready if wait asserted at zero
762
 
763
 
764
 
765
 
766
 
767
 
768
 
769
THRESHOLD_AUX <= '0' & THRESHOLD;
770
 
771
 
772
 
773
 
774
 
775
 
776
 
777
 
778
 
779
 
780
 
781
end STRUCTURAL;
782
 

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