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Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [coregen/] [coregen.cgc] - Blame information for rev 9

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   xilinx.com
   project
   coregen
   1.0
   
      
         DP_RAM_XILINX_256
         
         
            DP_RAM_XILINX_256
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Simple_Dual_Port_RAM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            32
            256
            32
            WRITE_FIRST
            Always_Enabled
            32
            32
            WRITE_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7vx485t
                  virtex7
                  ffg1761
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
      
         DP_RAM_XILINX_512
         
         
            DP_RAM_XILINX_512
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Simple_Dual_Port_RAM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            32
            512
            32
            WRITE_FIRST
            Always_Enabled
            32
            32
            WRITE_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7vx485t
                  virtex7
                  ffg1761
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
      
         DP_RAM_XILINX_MASK
         
         
            DP_RAM_XILINX_MASK
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Simple_Dual_Port_RAM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            4
            256
            4
            WRITE_FIRST
            Always_Enabled
            4
            4
            WRITE_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7vx485t
                  virtex7
                  ffg1761
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc7vx485t
            virtex7
            ffg1761
            -2
         
         
            BusFormatAngleBracketNotRipped
            VHDL
            true
            Other
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            VHDL
            false
         
      
   

 

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Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [coregen/] [coregen.cgc] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	eejlny
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`DP_RAM_XILINX_256`
10
11
12			`DP_RAM_XILINX_256`
13			`Native`
14			`AXI4_Full`
15			`Memory_Slave`
16			`false`
17			`4`
18			`Simple_Dual_Port_RAM`
19			`false`
20			`No_ECC`
21			`false`
22			`false`
23			`false`
24			`Single_Bit_Error_Injection`
25			`false`
26			`9`
27			`Minimum_Area`
28			`8kx2`
29			`false`
30			`32`
31			`256`
32			`32`
33			`WRITE_FIRST`
34			`Always_Enabled`
35			`32`
36			`32`
37			`WRITE_FIRST`
38			`Use_ENB_Pin`
39			`false`
40			`false`
41			`false`
42			`false`
43			`false`
44			`false`
45			`false`
46			`false`
47			`0`
48			`false`
49			`no_coe_file_loaded`
50			`false`
51			`0`
52			`false`
53			`false`
54			`CE`
55			`0`
56			`false`
57			`false`
58			`CE`
59			`0`
60			`SYNC`
61			`false`
62			`100`
63			`50`
64			`100`
65			`0`
66			`100`
67			`100`
68			`ALL`
69			`false`
70			`false`
71			`Stand_Alone`
72			`no_Mem_file_loaded`
73
74
75
76
77			`coregen`
78			`./`
79			`./tmp/`
80			`./tmp/_cg/`
81
82
83			`xc7vx485t`
84			`virtex7`
85			`ffg1761`
86			`-2`
87
88
89			`BusFormatAngleBracketNotRipped`
90			`VHDL`
91			`true`
92			`Other`
93			`false`
94			`false`
95			`false`
96			`Ngc`
97			`false`
98
99
100			`Behavioral`
101			`VHDL`
102			`false`
103
104
105			`2012-11-19+16:22`
106
107
108
109
110
111			`DP_RAM_XILINX_512`
112
113
114			`DP_RAM_XILINX_512`
115			`Native`
116			`AXI4_Full`
117			`Memory_Slave`
118			`false`
119			`4`
120			`Simple_Dual_Port_RAM`
121			`false`
122			`No_ECC`
123			`false`
124			`false`
125			`false`
126			`Single_Bit_Error_Injection`
127			`false`
128			`9`
129			`Minimum_Area`
130			`8kx2`
131			`false`
132			`32`
133			`512`
134			`32`
135			`WRITE_FIRST`
136			`Always_Enabled`
137			`32`
138			`32`
139			`WRITE_FIRST`
140			`Use_ENB_Pin`
141			`false`
142			`false`
143			`false`
144			`false`
145			`false`
146			`false`
147			`false`
148			`false`
149			`0`
150			`false`
151			`no_coe_file_loaded`
152			`false`
153			`0`
154			`false`
155			`false`
156			`CE`
157			`0`
158			`false`
159			`false`
160			`CE`
161			`0`
162			`SYNC`
163			`false`
164			`100`
165			`50`
166			`100`
167			`0`
168			`100`
169			`100`
170			`ALL`
171			`false`
172			`false`
173			`Stand_Alone`
174			`no_Mem_file_loaded`
175
176
177
178
179			`coregen`
180			`./`
181			`./tmp/`
182			`./tmp/_cg/`
183
184
185			`xc7vx485t`
186			`virtex7`
187			`ffg1761`
188			`-2`
189
190
191			`BusFormatAngleBracketNotRipped`
192			`VHDL`
193			`true`
194			`Other`
195			`false`
196			`false`
197			`false`
198			`Ngc`
199			`false`
200
201
202			`Behavioral`
203			`VHDL`
204			`false`
205
206
207			`2012-11-19+16:22`
208
209
210
211
212
213			`DP_RAM_XILINX_MASK`
214
215
216			`DP_RAM_XILINX_MASK`
217			`Native`
218			`AXI4_Full`
219			`Memory_Slave`
220			`false`
221			`4`
222			`Simple_Dual_Port_RAM`
223			`false`
224			`No_ECC`
225			`false`
226			`false`
227			`false`
228			`Single_Bit_Error_Injection`
229			`false`
230			`9`
231			`Minimum_Area`
232			`8kx2`
233			`false`
234			`4`
235			`256`
236			`4`
237			`WRITE_FIRST`
238			`Always_Enabled`
239			`4`
240			`4`
241			`WRITE_FIRST`
242			`Use_ENB_Pin`
243			`false`
244			`false`
245			`false`
246			`false`
247			`false`
248			`false`
249			`false`
250			`false`
251			`0`
252			`false`
253			`no_coe_file_loaded`
254			`false`
255			`0`
256			`false`
257			`false`
258			`CE`
259			`0`
260			`false`
261			`false`
262			`CE`
263			`0`
264			`SYNC`
265			`false`
266			`100`
267			`50`
268			`100`
269			`0`
270			`100`
271			`100`
272			`ALL`
273			`false`
274			`false`
275			`Stand_Alone`
276			`no_Mem_file_loaded`
277
278
279
280
281			`coregen`
282			`./`
283			`./tmp/`
284			`./tmp/_cg/`
285
286
287			`xc7vx485t`
288			`virtex7`
289			`ffg1761`
290			`-2`
291
292
293			`BusFormatAngleBracketNotRipped`
294			`VHDL`
295			`true`
296			`Other`
297			`false`
298			`false`
299			`false`
300			`Ngc`
301			`false`
302
303
304			`Behavioral`
305			`VHDL`
306			`false`
307
308
309			`2012-11-19+16:22`
310
311
312
313
314
315
316
317
318			`coregen`
319			`./`
320			`./tmp/`
321			`./tmp/_cg/`
322
323
324			`xc7vx485t`
325			`virtex7`
326			`ffg1761`
327			`-2`
328
329
330			`BusFormatAngleBracketNotRipped`
331			`VHDL`
332			`true`
333			`Other`
334			`false`
335			`false`
336			`false`
337			`Ngc`
338			`false`
339
340
341			`Behavioral`
342			`VHDL`
343			`false`
344
345
346
347
348