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rem Clean up the results directory

rmdir /S /Q results

mkdir results

rem Synthesize the VHDL Wrapper Files

#Synthesize the Wrapper Files

echo 'Synthesizing example design with XST';

xst -ifn xst.scr

copy fifo_32x512_exdes.ngc .\results\

rem Copy the netlist generated by Coregen

echo 'Copying files from the netlist directory to the results directory'

copy ..\..\fifo_32x512.ngc results\

rem  Copy the constraints files generated by Coregen

echo 'Copying files from constraints directory to results directory'

copy ..\example_design\fifo_32x512_exdes.ucf results\

cd results

echo 'Running ngdbuild'

ngdbuild -p xc7vx485t-ffg1761-2 -sd ../../../ fifo_32x512_exdes

echo 'Running map'

map fifo_32x512_exdes -o mapped.ncd

echo 'Running par'

par mapped.ncd routed.ncd

echo 'Running trce'

trce -e 10 routed.ncd mapped.pcf -o routed

echo 'Running design through bitgen'

bitgen -w routed -g UnconstrainedPins:Allow

echo 'Running netgen to create gate level VHDL model'

netgen -ofmt vhdl -sim -tm fifo_32x512_exdes -pcf mapped.pcf -w routed.ncd routed.vhd