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--
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-- FIFO Generator Core Demo Testbench
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: fifo_32x512_dgen.vhd
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--
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-- Description:
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-- Used for write interface stimulus generation
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE IEEE.std_logic_arith.all;
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USE IEEE.std_logic_misc.all;
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LIBRARY work;
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USE work.fifo_32x512_pkg.ALL;
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ENTITY fifo_32x512_dgen IS
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GENERIC (
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C_DIN_WIDTH : INTEGER := 32;
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C_DOUT_WIDTH : INTEGER := 32;
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C_CH_TYPE : INTEGER := 0;
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TB_SEED : INTEGER := 2
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);
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PORT (
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RESET : IN STD_LOGIC;
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WR_CLK : IN STD_LOGIC;
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PRC_WR_EN : IN STD_LOGIC;
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FULL : IN STD_LOGIC;
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WR_EN : OUT STD_LOGIC;
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WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE fg_dg_arch OF fifo_32x512_dgen IS
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CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
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CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
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SIGNAL pr_w_en : STD_LOGIC := '0';
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SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
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SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
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BEGIN
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WR_EN <= PRC_WR_EN ;
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WR_DATA <= wr_data_i AFTER 100 ns;
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----------------------------------------------
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-- Generation of DATA
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----------------------------------------------
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gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
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rd_gen_inst1:fifo_32x512_rng
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GENERIC MAP(
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WIDTH => 8,
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SEED => TB_SEED+N
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)
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PORT MAP(
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CLK => WR_CLK,
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RESET => RESET,
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RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
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ENABLE => pr_w_en
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);
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END GENERATE;
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pr_w_en <= PRC_WR_EN AND NOT FULL;
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wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
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END ARCHITECTURE;
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