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--
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-- FIFO Generator Core Demo Testbench
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: fifo_32x512_pkg.vhd
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--
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-- Description:
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-- This is the demo testbench package file for FIFO Generator core.
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE ieee.std_logic_arith.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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PACKAGE fifo_32x512_pkg IS
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FUNCTION divroundup (
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data_value : INTEGER;
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divisor : INTEGER)
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RETURN INTEGER;
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------------------------
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FUNCTION if_then_else (
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condition : BOOLEAN;
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true_case : INTEGER;
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false_case : INTEGER)
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RETURN INTEGER;
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------------------------
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FUNCTION if_then_else (
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condition : BOOLEAN;
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true_case : STD_LOGIC;
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false_case : STD_LOGIC)
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RETURN STD_LOGIC;
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------------------------
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FUNCTION if_then_else (
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condition : BOOLEAN;
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true_case : TIME;
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false_case : TIME)
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RETURN TIME;
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------------------------
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FUNCTION log2roundup (
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data_value : INTEGER)
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RETURN INTEGER;
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------------------------
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FUNCTION hexstr_to_std_logic_vec(
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arg1 : string;
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size : integer )
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RETURN std_logic_vector;
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------------------------
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COMPONENT fifo_32x512_rng IS
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GENERIC (WIDTH : integer := 8;
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SEED : integer := 3);
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PORT (
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CLK : IN STD_LOGIC;
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RESET : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
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);
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END COMPONENT;
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------------------------
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COMPONENT fifo_32x512_dgen IS
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GENERIC (
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C_DIN_WIDTH : INTEGER := 32;
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C_DOUT_WIDTH : INTEGER := 32;
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C_CH_TYPE : INTEGER := 0;
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TB_SEED : INTEGER := 2
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);
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PORT (
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RESET : IN STD_LOGIC;
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WR_CLK : IN STD_LOGIC;
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PRC_WR_EN : IN STD_LOGIC;
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FULL : IN STD_LOGIC;
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WR_EN : OUT STD_LOGIC;
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WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
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);
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END COMPONENT;
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------------------------
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COMPONENT fifo_32x512_dverif IS
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GENERIC(
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C_DIN_WIDTH : INTEGER := 0;
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C_DOUT_WIDTH : INTEGER := 0;
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C_USE_EMBEDDED_REG : INTEGER := 0;
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C_CH_TYPE : INTEGER := 0;
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TB_SEED : INTEGER := 2
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);
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PORT(
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RESET : IN STD_LOGIC;
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RD_CLK : IN STD_LOGIC;
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PRC_RD_EN : IN STD_LOGIC;
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EMPTY : IN STD_LOGIC;
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DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
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RD_EN : OUT STD_LOGIC;
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DOUT_CHK : OUT STD_LOGIC
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);
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END COMPONENT;
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------------------------
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COMPONENT fifo_32x512_pctrl IS
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GENERIC(
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AXI_CHANNEL : STRING := "NONE";
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C_APPLICATION_TYPE : INTEGER := 0;
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C_DIN_WIDTH : INTEGER := 0;
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C_DOUT_WIDTH : INTEGER := 0;
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C_WR_PNTR_WIDTH : INTEGER := 0;
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C_RD_PNTR_WIDTH : INTEGER := 0;
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C_CH_TYPE : INTEGER := 0;
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FREEZEON_ERROR : INTEGER := 0;
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TB_STOP_CNT : INTEGER := 2;
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TB_SEED : INTEGER := 2
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);
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PORT(
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RESET_WR : IN STD_LOGIC;
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RESET_RD : IN STD_LOGIC;
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WR_CLK : IN STD_LOGIC;
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RD_CLK : IN STD_LOGIC;
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FULL : IN STD_LOGIC;
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EMPTY : IN STD_LOGIC;
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ALMOST_FULL : IN STD_LOGIC;
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ALMOST_EMPTY : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
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DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
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DOUT_CHK : IN STD_LOGIC;
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PRC_WR_EN : OUT STD_LOGIC;
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PRC_RD_EN : OUT STD_LOGIC;
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RESET_EN : OUT STD_LOGIC;
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SIM_DONE : OUT STD_LOGIC;
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STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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------------------------
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COMPONENT fifo_32x512_synth IS
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GENERIC(
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FREEZEON_ERROR : INTEGER := 0;
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TB_STOP_CNT : INTEGER := 0;
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TB_SEED : INTEGER := 1
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);
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PORT(
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WR_CLK : IN STD_LOGIC;
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RD_CLK : IN STD_LOGIC;
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RESET : IN STD_LOGIC;
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SIM_DONE : OUT STD_LOGIC;
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STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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------------------------
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COMPONENT fifo_32x512_exdes IS
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PORT (
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WR_CLK : IN std_logic;
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RD_CLK : IN std_logic;
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ALMOST_FULL : OUT std_logic;
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RST : IN std_logic;
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WR_EN : IN std_logic;
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RD_EN : IN std_logic;
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DIN : IN std_logic_vector(32-1 DOWNTO 0);
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DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
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FULL : OUT std_logic;
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EMPTY : OUT std_logic);
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END COMPONENT;
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------------------------
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END fifo_32x512_pkg;
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PACKAGE BODY fifo_32x512_pkg IS
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FUNCTION divroundup (
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data_value : INTEGER;
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divisor : INTEGER)
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RETURN INTEGER IS
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VARIABLE div : INTEGER;
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BEGIN
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div := data_value/divisor;
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IF ( (data_value MOD divisor) /= 0) THEN
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div := div+1;
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END IF;
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RETURN div;
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END divroundup;
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---------------------------------
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FUNCTION if_then_else (
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condition : BOOLEAN;
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true_case : INTEGER;
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false_case : INTEGER)
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RETURN INTEGER IS
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VARIABLE retval : INTEGER := 0;
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BEGIN
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IF condition=false THEN
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retval:=false_case;
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ELSE
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retval:=true_case;
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END IF;
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RETURN retval;
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END if_then_else;
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---------------------------------
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FUNCTION if_then_else (
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condition : BOOLEAN;
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true_case : STD_LOGIC;
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false_case : STD_LOGIC)
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RETURN STD_LOGIC IS
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VARIABLE retval : STD_LOGIC := '0';
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BEGIN
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IF condition=false THEN
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retval:=false_case;
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ELSE
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retval:=true_case;
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END IF;
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RETURN retval;
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END if_then_else;
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---------------------------------
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FUNCTION if_then_else (
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condition : BOOLEAN;
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true_case : TIME;
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false_case : TIME)
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RETURN TIME IS
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VARIABLE retval : TIME := 0 ps;
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BEGIN
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IF condition=false THEN
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retval:=false_case;
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ELSE
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retval:=true_case;
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END IF;
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RETURN retval;
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END if_then_else;
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-------------------------------
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FUNCTION log2roundup (
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data_value : INTEGER)
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RETURN INTEGER IS
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VARIABLE width : INTEGER := 0;
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VARIABLE cnt : INTEGER := 1;
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BEGIN
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IF (data_value <= 1) THEN
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width := 1;
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ELSE
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WHILE (cnt < data_value) LOOP
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width := width + 1;
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cnt := cnt *2;
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END LOOP;
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END IF;
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RETURN width;
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END log2roundup;
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------------------------------------------------------------------------------
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-- hexstr_to_std_logic_vec
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-- This function converts a hex string to a std_logic_vector
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------------------------------------------------------------------------------
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FUNCTION hexstr_to_std_logic_vec(
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arg1 : string;
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size : integer )
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RETURN std_logic_vector IS
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VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
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VARIABLE bin : std_logic_vector(3 DOWNTO 0);
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VARIABLE index : integer := 0;
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BEGIN
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FOR i IN arg1'reverse_range LOOP
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CASE arg1(i) IS
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WHEN '0' => bin := (OTHERS => '0');
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WHEN '1' => bin := (0 => '1', OTHERS => '0');
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WHEN '2' => bin := (1 => '1', OTHERS => '0');
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WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
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WHEN '4' => bin := (2 => '1', OTHERS => '0');
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WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
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WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
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WHEN '7' => bin := (3 => '0', OTHERS => '1');
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WHEN '8' => bin := (3 => '1', OTHERS => '0');
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WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
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WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
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WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
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WHEN 'B' => bin := (2 => '0', OTHERS => '1');
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WHEN 'b' => bin := (2 => '0', OTHERS => '1');
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WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
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WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
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WHEN 'D' => bin := (1 => '0', OTHERS => '1');
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WHEN 'd' => bin := (1 => '0', OTHERS => '1');
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WHEN 'E' => bin := (0 => '0', OTHERS => '1');
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WHEN 'e' => bin := (0 => '0', OTHERS => '1');
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WHEN 'F' => bin := (OTHERS => '1');
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WHEN 'f' => bin := (OTHERS => '1');
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WHEN OTHERS =>
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FOR j IN 0 TO 3 LOOP
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bin(j) := 'X';
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END LOOP;
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END CASE;
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FOR j IN 0 TO 3 LOOP
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IF (index*4)+j < size THEN
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result((index*4)+j) := bin(j);
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END IF;
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END LOOP;
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index := index + 1;
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END LOOP;
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RETURN result;
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END hexstr_to_std_logic_vec;
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END fifo_32x512_pkg;
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