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CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
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Release Date: December 18, 2012
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Table of Contents
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1. INTRODUCTION
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2. DEVICE SUPPORT
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3. NEW FEATURE HISTORY
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4. RESOLVED ISSUES
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5. KNOWN ISSUES & LIMITATIONS
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6. TECHNICAL SUPPORT & FEEDBACK
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7. CORE RELEASE HISTORY
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8. LEGAL DISCLAIMER
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1. INTRODUCTION
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For installation instructions for this release, please go to:
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<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
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For system requirements:
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<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
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This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
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solution. For the latest core updates, see the product page at:
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<A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
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................................................................................
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2. DEVICE SUPPORT
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2.1 ISE
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The following device families are supported by the core for this release.
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All 7 Series devices
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Zynq-7000 devices
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All Virtex-6 devices
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All Spartan-6 devices
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All Virtex-5 devices
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All Spartan-3 devices
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All Virtex-4 devices
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2.2 Vivado
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All 7 Series devices
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Zynq-7000 devices
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3. NEW FEATURE HISTORY
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3.1 ISE
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- ISE 14.4 software support
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3.2 Vivado
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- 2012.4 software support
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- IP level constraint for Built-in FIFO reset synchronizer
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4. RESOLVED ISSUES
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4.1 ISE
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- N/A
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4.2 Vivado
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- N/A
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5. KNOWN ISSUES & LIMITATIONS
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5.1 ISE
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The following are known issues for v9.3 Rev 1 of this core at time of release:
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1. Importing an XCO file alters the XCO configurations
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Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
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into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
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page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
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CR 467240
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AR 31379
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2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
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Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
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correct behavior of the FIFO status flags cannot be guaranteed after the first write.
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Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
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For more information and additional workaround see Answer Record 41099.
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5.2 Vivado
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The following are known issues for v9.3 Rev 1 of this core at time of release:
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1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
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ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
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CR 665836
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The most recent information, including known issues, workarounds, and
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resolutions for this version is provided in the IP Release Notes User Guide
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located at
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<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
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6. TECHNICAL SUPPORT & FEEDBACK
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To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
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Questions are routed to a team with expertise using this product.
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Xilinx provides technical support for use of this product when used
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according to the guidelines described in the core documentation, and
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cannot guarantee timing, functionality, or support of this product for
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designs that do not follow specified guidelines.
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................................................................................
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7. CORE RELEASE HISTORY
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Date By Version Description
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================================================================================
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12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
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10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
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07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
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04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
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AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
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01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
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10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
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06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
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03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
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10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
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09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
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07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
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06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
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04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
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12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
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09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
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06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
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04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
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09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
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03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
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10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
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08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
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04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
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09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
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07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
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01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
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08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
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04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
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11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
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05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
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04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
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================================================================================
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8. LEGAL DISCLAIMER
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(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
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This file contains confidential and proprietary information
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of Xilinx, Inc. and is protected under U.S. and
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international copyright and other intellectual property
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laws.
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DISCLAIMER
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This disclaimer is not a license and does not grant any
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rights to the materials distributed herewith. Except as
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otherwise provided in a valid license issued to you by
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Xilinx, and to the maximum extent permitted by applicable
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law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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(2) Xilinx shall not be liable (whether in contract or tort,
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including negligence, or under any other theory of
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liability) for any loss or damage of any kind or nature
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related to, arising under or in connection with these
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materials, including for any direct, or any indirect,
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special, incidental, or consequential loss or damage
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(including loss of data, profits, goodwill, or any type of
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loss or damage suffered as a result of any action brought
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by a third party) even if such damage or loss was
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reasonably foreseeable or Xilinx had been advised of the
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possibility of the same.
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CRITICAL APPLICATIONS
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Xilinx products are not designed or intended to be fail-
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safe, or for use in any application requiring fail-safe
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performance, such as life-support or safety devices or
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systems, Class III medical devices, nuclear facilities,
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applications related to the deployment of airbags, or any
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other applications that could lead to death, personal
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injury, or severe property or environmental damage
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(individually and collectively, "Critical
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Applications"). Customer assumes the sole risk and
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liability of any use of Xilinx products in Critical
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Applications, subject only to applicable laws and
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regulations governing limitations on product liability.
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THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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PART OF THIS FILE AT ALL TIMES.
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