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--
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-- FIFO Generator Core Demo Testbench
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: fifo_generator_v9_3_pctrl.vhd
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--
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-- Description:
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-- Used for protocol control on write and read interface stimulus and status generation
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE IEEE.std_logic_arith.all;
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USE IEEE.std_logic_misc.all;
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LIBRARY work;
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USE work.fifo_generator_v9_3_pkg.ALL;
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ENTITY fifo_generator_v9_3_pctrl IS
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GENERIC(
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AXI_CHANNEL : STRING :="NONE";
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C_APPLICATION_TYPE : INTEGER := 0;
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C_DIN_WIDTH : INTEGER := 0;
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C_DOUT_WIDTH : INTEGER := 0;
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C_WR_PNTR_WIDTH : INTEGER := 0;
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C_RD_PNTR_WIDTH : INTEGER := 0;
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C_CH_TYPE : INTEGER := 0;
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FREEZEON_ERROR : INTEGER := 0;
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TB_STOP_CNT : INTEGER := 2;
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TB_SEED : INTEGER := 2
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);
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PORT(
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RESET_WR : IN STD_LOGIC;
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RESET_RD : IN STD_LOGIC;
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WR_CLK : IN STD_LOGIC;
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RD_CLK : IN STD_LOGIC;
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FULL : IN STD_LOGIC;
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EMPTY : IN STD_LOGIC;
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ALMOST_FULL : IN STD_LOGIC;
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ALMOST_EMPTY : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
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DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
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DOUT_CHK : IN STD_LOGIC;
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PRC_WR_EN : OUT STD_LOGIC;
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PRC_RD_EN : OUT STD_LOGIC;
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RESET_EN : OUT STD_LOGIC;
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SIM_DONE : OUT STD_LOGIC;
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STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE fg_pc_arch OF fifo_generator_v9_3_pctrl IS
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CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
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CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
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CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
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SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
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SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
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SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
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SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
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SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
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SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
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SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
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SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
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SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
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SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
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SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
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SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
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SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
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SIGNAL wr_en_i : STD_LOGIC := '0';
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SIGNAL rd_en_i : STD_LOGIC := '0';
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SIGNAL state : STD_LOGIC := '0';
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SIGNAL wr_control : STD_LOGIC := '0';
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SIGNAL rd_control : STD_LOGIC := '0';
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SIGNAL stop_on_err : STD_LOGIC := '0';
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SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
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SIGNAL sim_done_i : STD_LOGIC := '0';
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SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
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SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
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SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
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SIGNAL prc_we_i : STD_LOGIC := '0';
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SIGNAL prc_re_i : STD_LOGIC := '0';
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SIGNAL reset_en_i : STD_LOGIC := '0';
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SIGNAL state_d1 : STD_LOGIC := '0';
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SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
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SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
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BEGIN
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status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
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STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
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prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
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prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
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SIM_DONE <= sim_done_i;
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rdw_gt_wrw <= (OTHERS => '1');
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wrw_gt_rdw <= (OTHERS => '1');
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PROCESS(RD_CLK)
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BEGIN
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IF (RD_CLK'event AND RD_CLK='1') THEN
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IF(prc_re_i = '1') THEN
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rd_activ_cont <= rd_activ_cont + "1";
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END IF;
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END IF;
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END PROCESS;
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PROCESS(sim_done_i)
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BEGIN
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assert sim_done_i = '0'
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report "Simulation Complete for:" & AXI_CHANNEL
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severity note;
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END PROCESS;
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-----------------------------------------------------
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-- SIM_DONE SIGNAL GENERATION
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-----------------------------------------------------
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PROCESS (RD_CLK,RESET_RD)
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BEGIN
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IF(RESET_RD = '1') THEN
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--sim_done_i <= '0';
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ELSIF(RD_CLK'event AND RD_CLK='1') THEN
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IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
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sim_done_i <= '1';
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END IF;
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END IF;
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END PROCESS;
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-- TB Timeout/Stop
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fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
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PROCESS (RD_CLK)
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BEGIN
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IF (RD_CLK'event AND RD_CLK='1') THEN
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IF(state = '0' AND state_d1 = '1') THEN
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sim_stop_cntr <= sim_stop_cntr - "1";
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END IF;
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END IF;
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END PROCESS;
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END GENERATE fifo_tb_stop_run;
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-- Stop when error found
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PROCESS (RD_CLK)
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BEGIN
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IF (RD_CLK'event AND RD_CLK='1') THEN
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IF(sim_done_i = '0') THEN
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status_d1_i <= status_i OR status_d1_i;
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END IF;
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IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
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stop_on_err <= '1';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------
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-----------------------------------------------------
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-- CHECKS FOR FIFO
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-----------------------------------------------------
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PROCESS(RD_CLK,RESET_RD)
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BEGIN
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IF(RESET_RD = '1') THEN
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post_rst_dly_rd <= (OTHERS => '1');
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ELSIF (RD_CLK'event AND RD_CLK='1') THEN
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post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
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END IF;
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END PROCESS;
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PROCESS(WR_CLK,RESET_WR)
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BEGIN
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IF(RESET_WR = '1') THEN
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post_rst_dly_wr <= (OTHERS => '1');
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ELSIF (WR_CLK'event AND WR_CLK='1') THEN
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post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
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END IF;
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END PROCESS;
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-- FULL de-assert Counter
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PROCESS(WR_CLK,RESET_WR)
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BEGIN
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IF(RESET_WR = '1') THEN
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full_ds_timeout <= (OTHERS => '0');
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ELSIF(WR_CLK'event AND WR_CLK='1') THEN
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IF(state = '1') THEN
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IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
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full_ds_timeout <= full_ds_timeout + '1';
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END IF;
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ELSE
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full_ds_timeout <= (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS;
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-- EMPTY deassert counter
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PROCESS(RD_CLK,RESET_RD)
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BEGIN
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IF(RESET_RD = '1') THEN
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empty_ds_timeout <= (OTHERS => '0');
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ELSIF(RD_CLK'event AND RD_CLK='1') THEN
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IF(state = '0') THEN
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IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
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empty_ds_timeout <= empty_ds_timeout + '1';
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END IF;
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ELSE
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empty_ds_timeout <= (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS;
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-- Full check signal generation
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PROCESS(WR_CLK,RESET_WR)
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BEGIN
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IF(RESET_WR = '1') THEN
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full_chk_i <= '0';
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ELSIF(WR_CLK'event AND WR_CLK='1') THEN
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IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
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full_chk_i <= '0';
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ELSE
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full_chk_i <= AND_REDUCE(full_as_timeout) OR
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AND_REDUCE(full_ds_timeout);
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END IF;
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END IF;
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END PROCESS;
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-- Empty checks
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PROCESS(RD_CLK,RESET_RD)
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BEGIN
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IF(RESET_RD = '1') THEN
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empty_chk_i <= '0';
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ELSIF(RD_CLK'event AND RD_CLK='1') THEN
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IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
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empty_chk_i <= '0';
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ELSE
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empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
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AND_REDUCE(empty_ds_timeout);
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END IF;
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END IF;
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END PROCESS;
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fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
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PRC_WR_EN <= prc_we_i AFTER 50 ns;
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PRC_RD_EN <= prc_re_i AFTER 50 ns;
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data_chk_i <= dout_chk;
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END GENERATE fifo_d_chk;
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-----------------------------------------------------
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RESET_EN <= reset_en_i;
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PROCESS(RD_CLK,RESET_RD)
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BEGIN
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IF(RESET_RD = '1') THEN
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state_d1 <= '0';
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ELSIF (RD_CLK'event AND RD_CLK='1') THEN
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state_d1 <= state;
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END IF;
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END PROCESS;
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
|
317 |
|
|
-----------------------------------------------------
|
318 |
|
|
-- WR_EN GENERATION
|
319 |
|
|
-----------------------------------------------------
|
320 |
|
|
gen_rand_wr_en:fifo_generator_v9_3_rng
|
321 |
|
|
GENERIC MAP(
|
322 |
|
|
WIDTH => 8,
|
323 |
|
|
SEED => TB_SEED+1
|
324 |
|
|
)
|
325 |
|
|
PORT MAP(
|
326 |
|
|
CLK => WR_CLK,
|
327 |
|
|
RESET => RESET_WR,
|
328 |
|
|
RANDOM_NUM => wr_en_gen,
|
329 |
|
|
ENABLE => '1'
|
330 |
|
|
);
|
331 |
|
|
|
332 |
|
|
PROCESS(WR_CLK,RESET_WR)
|
333 |
|
|
BEGIN
|
334 |
|
|
IF(RESET_WR = '1') THEN
|
335 |
|
|
wr_en_i <= '0';
|
336 |
|
|
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
337 |
|
|
IF(state = '1') THEN
|
338 |
|
|
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
|
339 |
|
|
ELSE
|
340 |
|
|
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
|
341 |
|
|
END IF;
|
342 |
|
|
END IF;
|
343 |
|
|
END PROCESS;
|
344 |
|
|
|
345 |
|
|
-----------------------------------------------------
|
346 |
|
|
-- WR_EN CONTROL
|
347 |
|
|
-----------------------------------------------------
|
348 |
|
|
PROCESS(WR_CLK,RESET_WR)
|
349 |
|
|
BEGIN
|
350 |
|
|
IF(RESET_WR = '1') THEN
|
351 |
|
|
wr_cntr <= (OTHERS => '0');
|
352 |
|
|
wr_control <= '1';
|
353 |
|
|
full_as_timeout <= (OTHERS => '0');
|
354 |
|
|
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
355 |
|
|
IF(state = '1') THEN
|
356 |
|
|
IF(wr_en_i = '1') THEN
|
357 |
|
|
wr_cntr <= wr_cntr + "1";
|
358 |
|
|
END IF;
|
359 |
|
|
full_as_timeout <= (OTHERS => '0');
|
360 |
|
|
ELSE
|
361 |
|
|
wr_cntr <= (OTHERS => '0');
|
362 |
|
|
IF(rd_en_i = '0') THEN
|
363 |
|
|
IF(wr_en_i = '1') THEN
|
364 |
|
|
full_as_timeout <= full_as_timeout + "1";
|
365 |
|
|
END IF;
|
366 |
|
|
ELSE
|
367 |
|
|
full_as_timeout <= (OTHERS => '0');
|
368 |
|
|
END IF;
|
369 |
|
|
END IF;
|
370 |
|
|
|
371 |
|
|
wr_control <= NOT wr_cntr(wr_cntr'high);
|
372 |
|
|
|
373 |
|
|
END IF;
|
374 |
|
|
END PROCESS;
|
375 |
|
|
|
376 |
|
|
-----------------------------------------------------
|
377 |
|
|
-- RD_EN GENERATION
|
378 |
|
|
-----------------------------------------------------
|
379 |
|
|
gen_rand_rd_en:fifo_generator_v9_3_rng
|
380 |
|
|
GENERIC MAP(
|
381 |
|
|
WIDTH => 8,
|
382 |
|
|
SEED => TB_SEED
|
383 |
|
|
)
|
384 |
|
|
PORT MAP(
|
385 |
|
|
CLK => RD_CLK,
|
386 |
|
|
RESET => RESET_RD,
|
387 |
|
|
RANDOM_NUM => rd_en_gen,
|
388 |
|
|
ENABLE => '1'
|
389 |
|
|
);
|
390 |
|
|
|
391 |
|
|
PROCESS(RD_CLK,RESET_RD)
|
392 |
|
|
BEGIN
|
393 |
|
|
IF(RESET_RD = '1') THEN
|
394 |
|
|
rd_en_i <= '0';
|
395 |
|
|
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
396 |
|
|
IF(state = '0') THEN
|
397 |
|
|
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
|
398 |
|
|
ELSE
|
399 |
|
|
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
|
400 |
|
|
END IF;
|
401 |
|
|
END IF;
|
402 |
|
|
END PROCESS;
|
403 |
|
|
|
404 |
|
|
-----------------------------------------------------
|
405 |
|
|
-- RD_EN CONTROL
|
406 |
|
|
-----------------------------------------------------
|
407 |
|
|
PROCESS(RD_CLK,RESET_RD)
|
408 |
|
|
BEGIN
|
409 |
|
|
IF(RESET_RD = '1') THEN
|
410 |
|
|
rd_cntr <= (OTHERS => '0');
|
411 |
|
|
rd_control <= '1';
|
412 |
|
|
empty_as_timeout <= (OTHERS => '0');
|
413 |
|
|
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
414 |
|
|
IF(state = '0') THEN
|
415 |
|
|
IF(rd_en_i = '1') THEN
|
416 |
|
|
rd_cntr <= rd_cntr + "1";
|
417 |
|
|
END IF;
|
418 |
|
|
empty_as_timeout <= (OTHERS => '0');
|
419 |
|
|
ELSE
|
420 |
|
|
rd_cntr <= (OTHERS => '0');
|
421 |
|
|
IF(wr_en_i = '0') THEN
|
422 |
|
|
IF(rd_en_i = '1') THEN
|
423 |
|
|
empty_as_timeout <= empty_as_timeout + "1";
|
424 |
|
|
END IF;
|
425 |
|
|
ELSE
|
426 |
|
|
empty_as_timeout <= (OTHERS => '0');
|
427 |
|
|
END IF;
|
428 |
|
|
END IF;
|
429 |
|
|
|
430 |
|
|
rd_control <= NOT rd_cntr(rd_cntr'high);
|
431 |
|
|
|
432 |
|
|
END IF;
|
433 |
|
|
END PROCESS;
|
434 |
|
|
|
435 |
|
|
-----------------------------------------------------
|
436 |
|
|
-- STIMULUS CONTROL
|
437 |
|
|
-----------------------------------------------------
|
438 |
|
|
PROCESS(WR_CLK,RESET_WR)
|
439 |
|
|
BEGIN
|
440 |
|
|
IF(RESET_WR = '1') THEN
|
441 |
|
|
state <= '0';
|
442 |
|
|
reset_en_i <= '0';
|
443 |
|
|
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
444 |
|
|
CASE state IS
|
445 |
|
|
WHEN '0' =>
|
446 |
|
|
IF(FULL = '1' AND EMPTY = '0') THEN
|
447 |
|
|
state <= '1';
|
448 |
|
|
reset_en_i <= '0';
|
449 |
|
|
END IF;
|
450 |
|
|
WHEN '1' =>
|
451 |
|
|
IF(EMPTY = '1' AND FULL = '0') THEN
|
452 |
|
|
state <= '0';
|
453 |
|
|
reset_en_i <= '1';
|
454 |
|
|
END IF;
|
455 |
|
|
WHEN OTHERS => state <= state;
|
456 |
|
|
END CASE;
|
457 |
|
|
END IF;
|
458 |
|
|
END PROCESS;
|
459 |
|
|
END GENERATE data_fifo_en;
|
460 |
|
|
|
461 |
|
|
END ARCHITECTURE;
|