URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [iseconfig/] [Fifo_test.projectmgr] - Blame information for rev 9

Details | Compare with Previous | View Log







   
   
      
         2
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/CODING_BUFFER - CODING_BUFFER_64_32 - STRUCTURAL
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/I_B - INPUT_BUFFER_32_32 - STRUCTURAL
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/P_U - PARSING_UNIT - STRUCTURAL
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/REG_FILE_1 - REG_FILE_C - LATCH
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/level2_4_1 - level2_4ca - level2_4ca
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/ASSEMBLING_UNIT_1 - ASSEMBLING_UNIT - STRUCTURAL
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/DECODING_BUFFER - DECODING_BUFFER_32_64_2 - STRUCTURAL
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/OUTPUT_BUFFER_32_32_1 - OUTPUT_BUFFER_32_32 - STRUCTURAL
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/REG_FILE_1 - REG_FILE_D - LATCH
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/level2_4_1 - level2_4d_pbc - level2_4d
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd/xmatchpro - level1r - level1_1
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/CODING_BUFFER - CODING_BUFFER_64_32 - STRUCTURAL
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/I_B - INPUT_BUFFER_32_32 - STRUCTURAL
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/P_U - PARSING_UNIT - STRUCTURAL
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/REG_FILE_1 - REG_FILE_C - LATCH
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/level2_4_1 - level2_4ca - level2_4ca
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/inst_xmatch - level1r - level1_1
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd/inst_xmatch - level1r - level1_1
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd/xmatchpro - level1r - level1_1
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1
      
      
         xmatch_controller - Behavioral (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c4000000020000000000000000000000000200000064ffffffff000000810000000300000002000002c40000000100000003000000000000000100000003
      true
      xmatch_controller - Behavioral (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd)
   
   
      
         1
         Configure Target Device
         Design Utilities
         Design Utilities/Compile HDL Simulation Libraries
         Implement Design/Map
         Implement Design/Place & Route
         Implement Design/Translate
         Synthesize - XST
         User Constraints
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000017f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000017f0000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff0000000000000001000000000000000001000000000000000000000000000000000000040a000000040101000100000000000000000000000064ffffffff000000810000000000000004000002690000000100000000000000d70000000100000000000000660000000100000000000000640000000100000000
      false
      assembler.vhd
   
   
      
         1
         dzx
      
      
      0
      0
      000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      dzx
   
   
      
         1
         User Constraints
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000263000000010000000100000000000000000000000064ffffffff000000810000000000000001000002630000000100000000
      false
      
   
   
      
         2
         /TB_LEVEL1cr - TB1cr C:|mohd|codmu_project|devl|xmatch_sim3|tb_level1cr.vhd
         /TB_LEVEL1cr - TB1cr C:|mohd|codmu_project|devl|xmatch_sim5|tb_level1cr.vhd
         /TB_LEVEL1cr - TB1cr C:|mohd|codmu_project|devl|xmatch_sim7|tb_level1cr.vhd
         /fifo_test_tb - behavior C:|mohd|Fifo_test|fifo_test_tb.vhd/uut - fifo_test - Behavioral
         /fifo_test_tb - behavior C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test_tb.vhd
         /fifo_test_tb - behavior C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test_tb.vhd
         /fifo_test_tb - behavior C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test_tb.vhd
         /testbench - behavior C:|Users|eejlny|projects|xmatch_sim7|xmatch_sim7|tb.vhd
         /testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim3|tb.vhd
         /testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim3|tb.vhd/uut - top - Behavioral
         /testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim5|tb.vhd
         /testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim5|tb.vhd/uut - xmatchpro - Behavioral/xmatchpro - level1r - level1_1
         /testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim7|tb.vhd/uut - xmatch_controller - Behavioral/xmatchpro - level1r - level1_1
         /top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd
         /xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd
         /xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd
      
      
         testbench - behavior (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000de000000020000000000000000000000000200000064ffffffff000000810000000300000002000000de0000000100000003000000000000000100000003
      true
      testbench - behavior (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd)
   
   
      
         1
         Design Utilities/Compile HDL Simulation Libraries
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
      false
      
   
   
      
         1
      
      
         ISim Simulator
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000017f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000017f0000000100000000
      false
      ISim Simulator
   
   
      
         1
         Configure Target Device
         Design Utilities/Compile HDL Simulation Libraries
         Implement Design
         Synthesize - XST
         User Constraints
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000219000000010000000100000000000000000000000064ffffffff000000810000000000000001000002190000000100000000
      false
      
   
   000000ff00000000000000020000011b0000011b01000000050100000002
   Behavioral Simulation
   
      
         1
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000196000000010000000100000000000000000000000064ffffffff000000810000000000000001000001960000000100000000
      false
      
   
   
      
         1
      
      
         
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000122000000010000000100000000000000000000000064ffffffff000000810000000000000001000001220000000100000000
      false
      
   


Browse

Tools

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [iseconfig/] [Fifo_test.projectmgr] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	eejlny
2
3
4
5
6
7
8
9			`2`
10			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1`
11			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/CODING_BUFFER - CODING_BUFFER_64_32 - STRUCTURAL`
12			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/I_B - INPUT_BUFFER_32_32 - STRUCTURAL`
13			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/P_U - PARSING_UNIT - STRUCTURAL`
14			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/REG_FILE_1 - REG_FILE_C - LATCH`
15			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/level2_4_1 - level2_4ca - level2_4ca`
16			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/ASSEMBLING_UNIT_1 - ASSEMBLING_UNIT - STRUCTURAL`
17			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/DECODING_BUFFER - DECODING_BUFFER_32_64_2 - STRUCTURAL`
18			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/OUTPUT_BUFFER_32_32_1 - OUTPUT_BUFFER_32_32 - STRUCTURAL`
19			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/REG_FILE_1 - REG_FILE_D - LATCH`
20			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/level2_4_1 - level2_4d_pbc - level2_4d`
21			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|fifo_test.vhd/xmatchpro - level1r - level1_1`
22			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1`
23			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/CODING_BUFFER - CODING_BUFFER_64_32 - STRUCTURAL`
24			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/I_B - INPUT_BUFFER_32_32 - STRUCTURAL`
25			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/P_U - PARSING_UNIT - STRUCTURAL`
26			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/REG_FILE_1 - REG_FILE_C - LATCH`
27			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/level2_4_1 - level2_4ca - level2_4ca`
28			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1`
29			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/inst_xmatch - level1r - level1_1`
30			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd/xmatchpro - level1r - level1_1`
31			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|fifo_test.vhd/inst_xmatch - level1r - level1_1`
32			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|fifo_test.vhd/xmatchpro - level1r - level1_1`
33			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd/xmatchpro - level1r - level1_1`
34
35
36			`xmatch_controller - Behavioral (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd)`
37
38			`0`
39			`0`
40			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c4000000020000000000000000000000000200000064ffffffff000000810000000300000002000002c40000000100000003000000000000000100000003`
41			`true`
42			`xmatch_controller - Behavioral (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd)`
43
44
45
46			`1`
47			`Configure Target Device`
48			`Design Utilities`
49			`Design Utilities/Compile HDL Simulation Libraries`
50			`Implement Design/Map`
51			`Implement Design/Place & Route`
52			`Implement Design/Translate`
53			`Synthesize - XST`
54			`User Constraints`
55
56
57
58
59			`0`
60			`0`
61			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000017f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000017f0000000100000000`
62			`false`
63
64
65
66
67			`1`
68
69
70			`0`
71			`0`
72			`000000ff0000000000000001000000000000000001000000000000000000000000000000000000040a000000040101000100000000000000000000000064ffffffff000000810000000000000004000002690000000100000000000000d70000000100000000000000660000000100000000000000640000000100000000`
73			`false`
74			`assembler.vhd`
75
76
77
78			`1`
79			`dzx`
80
81
82			`0`
83			`0`
84			`000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
85			`false`
86			`dzx`
87
88
89
90			`1`
91			`User Constraints`
92
93
94
95
96			`0`
97			`0`
98			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000263000000010000000100000000000000000000000064ffffffff000000810000000000000001000002630000000100000000`
99			`false`
100
101
102
103
104			`2`
105			`/TB_LEVEL1cr - TB1cr C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|tb_level1cr.vhd`
106			`/TB_LEVEL1cr - TB1cr C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|tb_level1cr.vhd`
107			`/TB_LEVEL1cr - TB1cr C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|tb_level1cr.vhd`
108			`/fifo_test_tb - behavior C:\|mohd\|Fifo_test\|fifo_test_tb.vhd/uut - fifo_test - Behavioral`
109			`/fifo_test_tb - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test_tb.vhd`
110			`/fifo_test_tb - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|fifo_test_tb.vhd`
111			`/fifo_test_tb - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test_tb.vhd`
112			`/testbench - behavior C:\|Users\|eejlny\|projects\|xmatch_sim7\|xmatch_sim7\|tb.vhd`
113			`/testbench - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|tb.vhd`
114			`/testbench - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|tb.vhd/uut - top - Behavioral`
115			`/testbench - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|tb.vhd`
116			`/testbench - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|tb.vhd/uut - xmatchpro - Behavioral/xmatchpro - level1r - level1_1`
117			`/testbench - behavior C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|tb.vhd/uut - xmatch_controller - Behavioral/xmatchpro - level1r - level1_1`
118			`/top - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd`
119			`/xmatch_controller - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim5\|fifo_test.vhd`
120			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim3\|fifo_test.vhd`
121			`/xmatchpro - Behavioral C:\|mohd\|codmu_project\|devl\|xmatch_sim7\|fifo_test.vhd`
122
123
124			`testbench - behavior (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd)`
125
126			`0`
127			`0`
128			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000de000000020000000000000000000000000200000064ffffffff000000810000000300000002000000de0000000100000003000000000000000100000003`
129			`true`
130			`testbench - behavior (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd)`
131
132
133
134			`1`
135			`Design Utilities/Compile HDL Simulation Libraries`
136
137
138
139
140			`0`
141			`0`
142			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000`
143			`false`
144
145
146
147
148			`1`
149
150
151			`ISim Simulator`
152
153			`0`
154			`0`
155			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000017f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000017f0000000100000000`
156			`false`
157			`ISim Simulator`
158
159
160
161			`1`
162			`Configure Target Device`
163			`Design Utilities/Compile HDL Simulation Libraries`
164			`Implement Design`
165			`Synthesize - XST`
166			`User Constraints`
167
168
169
170
171			`0`
172			`0`
173			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000219000000010000000100000000000000000000000064ffffffff000000810000000000000001000002190000000100000000`
174			`false`
175
176
177			`000000ff00000000000000020000011b0000011b01000000050100000002`
178			`Behavioral Simulation`
179
180
181			`1`
182
183
184
185
186			`0`
187			`0`
188			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000196000000010000000100000000000000000000000064ffffffff000000810000000000000001000001960000000100000000`
189			`false`
190
191
192
193
194			`1`
195
196
197
198
199			`0`
200			`0`
201			`000000ff00000000000000010000000100000000000000000000000000000000000000000000000122000000010000000100000000000000000000000064ffffffff000000810000000000000001000001220000000100000000`
202			`false`
203
204
205