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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [lib/] [xil_lib/] [DP_RAM_XILINX_256.vhd] - Blame information for rev 9

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1 9 eejlny
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--    This file is owned and controlled by Xilinx and must be used solely     --
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--    for design, simulation, implementation and creation of design files     --
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--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
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--    devices or technologies is expressly prohibited and immediately         --
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--    terminates your license.                                                --
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--                                                                            --
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--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
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--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
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--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
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--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
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--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
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--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
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--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
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--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
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--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
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--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
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--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
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--    PARTICULAR PURPOSE.                                                     --
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--                                                                            --
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--    Xilinx products are not intended for use in life support appliances,    --
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--    devices, or systems.  Use in such applications are expressly            --
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--    prohibited.                                                             --
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--                                                                            --
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--    (c) Copyright 1995-2015 Xilinx, Inc.                                    --
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--    All rights reserved.                                                    --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file DP_RAM_XILINX_256.vhd when simulating
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-- the core, DP_RAM_XILINX_256. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY DP_RAM_XILINX_256 IS
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  PORT (
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    clka : IN STD_LOGIC;
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    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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    clkb : IN STD_LOGIC;
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    enb : IN STD_LOGIC;
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    addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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  );
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END DP_RAM_XILINX_256;
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ARCHITECTURE DP_RAM_XILINX_256_a OF DP_RAM_XILINX_256 IS
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-- synthesis translate_off
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COMPONENT wrapped_DP_RAM_XILINX_256
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  PORT (
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    clka : IN STD_LOGIC;
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    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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    clkb : IN STD_LOGIC;
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    enb : IN STD_LOGIC;
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    addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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  );
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END COMPONENT;
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-- Configuration specification
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  FOR ALL : wrapped_DP_RAM_XILINX_256 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
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    GENERIC MAP (
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      c_addra_width => 8,
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      c_addrb_width => 8,
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      c_algorithm => 1,
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      c_axi_id_width => 4,
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      c_axi_slave_type => 0,
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      c_axi_type => 1,
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      c_byte_size => 9,
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      c_common_clk => 0,
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      c_default_data => "0",
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      c_disable_warn_bhv_coll => 0,
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      c_disable_warn_bhv_range => 0,
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      c_enable_32bit_address => 0,
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      c_family => "virtex7",
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      c_has_axi_id => 0,
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      c_has_ena => 0,
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      c_has_enb => 1,
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      c_has_injecterr => 0,
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      c_has_mem_output_regs_a => 0,
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      c_has_mem_output_regs_b => 0,
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      c_has_mux_output_regs_a => 0,
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      c_has_mux_output_regs_b => 0,
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      c_has_regcea => 0,
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      c_has_regceb => 0,
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      c_has_rsta => 0,
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      c_has_rstb => 0,
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      c_has_softecc_input_regs_a => 0,
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      c_has_softecc_output_regs_b => 0,
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      c_init_file => "BlankString",
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      c_init_file_name => "no_coe_file_loaded",
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      c_inita_val => "0",
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      c_initb_val => "0",
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      c_interface_type => 0,
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      c_load_init_file => 0,
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      c_mem_type => 1,
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      c_mux_pipeline_stages => 0,
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      c_prim_type => 1,
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      c_read_depth_a => 256,
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      c_read_depth_b => 256,
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      c_read_width_a => 32,
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      c_read_width_b => 32,
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      c_rst_priority_a => "CE",
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      c_rst_priority_b => "CE",
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      c_rst_type => "SYNC",
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      c_rstram_a => 0,
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      c_rstram_b => 0,
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      c_sim_collision_check => "ALL",
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      c_use_bram_block => 0,
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      c_use_byte_wea => 0,
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      c_use_byte_web => 0,
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      c_use_default_data => 0,
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      c_use_ecc => 0,
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      c_use_softecc => 0,
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      c_wea_width => 1,
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      c_web_width => 1,
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      c_write_depth_a => 256,
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      c_write_depth_b => 256,
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      c_write_mode_a => "WRITE_FIRST",
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      c_write_mode_b => "WRITE_FIRST",
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      c_write_width_a => 32,
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      c_write_width_b => 32,
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      c_xdevicefamily => "virtex7"
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    );
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_DP_RAM_XILINX_256
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  PORT MAP (
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    clka => clka,
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    wea => wea,
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    addra => addra,
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    dina => dina,
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    clkb => clkb,
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    enb => enb,
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    addrb => addrb,
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    doutb => doutb
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  );
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-- synthesis translate_on
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END DP_RAM_XILINX_256_a;

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