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--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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---------------------------------------------
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-- ENTITY = INPUT_BUFFER_32_32 --
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-- version = 1.0 --
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-- last update = 30/05/00 --
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-- author = Jose Nunez --
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---------------------------------------------
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-- FUNCTION
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-- This input buffer loads 32 bits of data from the input bus and writes 32 bit of data to the parsing unit
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-- 256x32 bit word to handle a block of 1 Kbyte. Then the buffer waits for the all data processed signal before requesting more data.
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-- PIN LIST
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-- START = activate the buffer
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-- FINISHED = the buffer block has been process in the engine. load more data if required
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-- READY = data ready to be processed in the buffer.
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-- DATA_IN_32 = input data from the 32 bit input bus
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-- BUS_ACKNOWLEDGE = Data is available in the input bus.
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-- DATA_OUT_32 = output data to the 32 bit wide output bus
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-- EMPTY = all the data present in the buffer has been processed
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-- BUS_REQUEST = output requesting data to be processed
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-- CLEAR = asynchronous clear
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-- CLK = master clock
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library ieee,dzx;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use dzx.bit_arith.all;
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library xil_lib;
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use xil_lib.xil_comp.all;
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use work.tech_package.all;
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entity INPUT_BUFFER_32_32 is
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port
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(
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OVERFLOW_CONTROL : in bit;
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FORCE_STOP : in bit;
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START : in bit;
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COMP : in bit;
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STOP : in bit;
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READ : in bit;
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WAITN : in bit;
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DATA_IN_32 : in bit_vector(31 downto 0);
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BUS_ACKNOWLEDGE : in bit;
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CLEAR : in bit ;
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CLK : in bit ;
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DATA_OUT_32: out bit_vector(31 downto 0);
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READY : out bit; -- data ready for the parser
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INC_TC : out bit;
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RESET_TOTAL_COUNTER : out bit;
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BUS_REQUEST : out bit
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);
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end INPUT_BUFFER_32_32;
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architecture STRUCTURAL of INPUT_BUFFER_32_32 is
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-- xilinx memory
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component DP_RAM_XILINX_256
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port (
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addra: IN std_logic_VECTOR(7 downto 0);
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clka: IN std_logic;
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addrb: IN std_logic_VECTOR(7 downto 0);
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clkb: IN std_logic;
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dina: IN std_logic_VECTOR(31 downto 0);
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wea: IN std_logic_vector (0 downto 0);
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enb: IN std_logic;
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doutb: OUT std_logic_VECTOR(31 downto 0));
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end component;
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-- Synplicity black box declaration
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--attribute black_box : boolean;
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--attribute black_box of DP_RAM_XILINX: component is true;
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-- Actel memory
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-- component MY_MEMORY
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-- port(DO : out std_logic_vector (31 downto 0);
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-- RCLOCK : in std_logic;
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-- WCLOCK : in std_logic;
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-- DI : in std_logic_vector (31 downto 0);
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-- WRB : in std_logic;
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-- RDB : in std_logic;
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-- WADDR : in std_logic_vector (7 downto 0);
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-- RADDR : in std_logic_vector (7 downto 0));
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--end component;
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--component syn_dpram_256x32_rawr
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--port (
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-- Data : in std_logic_vector(31 downto 0);
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-- RdAddress : in std_logic_vector(7 downto 0);
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-- WrAddress : in std_logic_vector(7 downto 0);
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-- RdEn : in std_logic;
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-- WrEn : in std_logic;
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-- Q : out std_logic_vector(31 downto 0);
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-- RdClock : in std_logic;
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-- RdClken : in std_logic;
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-- WrClock : in std_logic;
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-- WrClken : in std_logic
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-- );
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--end component;
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-- TSMC DPRAM
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component ra2sh_256W_32B_8MX_offWRMSK_8WRGRAN
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port (
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CLKA: in std_logic;
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CENA: in std_logic;
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WENA: in std_logic;
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AA: in std_logic_vector(7 downto 0);
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DA: in std_logic_vector(31 downto 0);
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QA: out std_logic_vector(31 downto 0);
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CLKB: in std_logic;
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CENB: in std_logic;
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WENB: in std_logic;
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AB: in std_logic_vector(7 downto 0);
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DB: in std_logic_vector(31 downto 0);
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QB: out std_logic_vector(31 downto 0)
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);
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end component;
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-- component LPM_RAM_DP
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-- generic (LPM_WIDTH : positive ;
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-- LPM_WIDTHAD : positive;
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-- LPM_NUMWORDS : positive;
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-- LPM_INDATA : string ;
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-- LPM_RDADDRESS_CONTROL : string ;
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-- LPM_WRADDRESS_CONTROL : string ;
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-- LPM_OUTDATA : string ;
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-- LPM_TYPE : string ;
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-- LPM_FILE : string ;
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-- LPM_HINT : string );
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-- port (RDCLOCK : in std_logic;
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-- RDCLKEN : in std_logic;
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-- RDADDRESS : in std_logic_vector(7 downto 0);
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-- RDEN : in std_logic;
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-- DATA : in std_logic_vector(31 downto 0);
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-- WRADDRESS : in std_logic_vector(7 downto 0);
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-- WREN : in std_logic;
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-- WRCLOCK : in std_logic;
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-- WRCLKEN : in std_logic;
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-- Q : out std_logic_vector(31 downto 0));
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--end component;
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--attribute noopt: boolean;
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--attribute noopt of LPM_RAM_DP: component is true;
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component INPUT_BUFFER_CU
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port (
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OVERFLOW_CONTROL : in bit;
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FORCE_STOP : in bit;
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START : in bit;
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STOP : in bit;
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BUS_ACKNOWLEDGE : in bit;
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WAITN : in bit;
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CODING_READ_ADDRESS : in bit_vector(7 downto 0);
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CODING_WRITE_ADDRESS : in bit_vector(7 downto 0);
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CLK : in bit;
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CLEAR : in bit;
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BUS_REQUEST : out bit;
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CLEAR_COUNTERS : out bit;
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RESET_TOTAL_COUNTER : out bit; -- only once per whole block
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ENABLE_PARSER : out bit;
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ENABLE_WRITE : out bit;
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ENABLE_READ : out bit
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);
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end component;
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component INPUT_COUNTER
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port (ENABLE : in bit;
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CLEAR : in bit;
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CLEAR_COUNTERS : in bit;
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CLK : in bit;
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COUNT : out bit_vector(7 downto 0)
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);
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end component;
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-- 1 bit for the 64-to-32 multiplexor
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signal CODING_READ_ADDRESS : bit_vector(7 downto 0);
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signal CODING_WRITE_ADDRESS : bit_vector(7 downto 0);
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signal ENABLE_WRITE : bit;
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signal ENABLE_READ : bit;
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signal DATA_OUT_AUX : std_logic_vector(31 downto 0);
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signal READ_CLK : bit;
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signal WRITE_CLK : bit;
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signal WRITE_CLK_ENABLE : bit;
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signal READ_CLK_ENABLE : bit;
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signal ENABLE_READ_INT : bit;
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signal ENABLE_WRITE_INT : bit;
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signal BUS_REQUEST_INT : bit;
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signal CLEAR_COUNTERS : bit;
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signal DATA_SB :std_logic_vector(31 downto 0);
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signal RDADDRESS_SB :std_logic_vector(7 downto 0);
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signal WRADDRESS_SB :std_logic_vector(7 downto 0);
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signal RDEN_SB :std_logic;
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signal WREN_SB :std_logic;
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signal RDCLOCK_SB :std_logic;
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signal RDCLKEN_SB :std_logic;
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signal WRCLOCK_SB :std_logic;
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signal WRCLKEN_SB :std_logic;
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signal READY_AUX : bit;
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signal ENABLE_WRITE_WITH_WAIT : bit;
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signal LOGIC_0 : std_logic := '0';
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signal tsmc_cena_n , tsmc_cenb_n : std_logic;
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signal tsmc_wena_n , tsmc_wenb_n : std_logic;
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begin
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CONTROL_UNIT : INPUT_BUFFER_CU
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port map(
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OVERFLOW_CONTROL => OVERFLOW_CONTROL,
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FORCE_STOP => FORCE_STOP,
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START => START,
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STOP => STOP,
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BUS_ACKNOWLEDGE => BUS_ACKNOWLEDGE,
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WAITN => WAITN,
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CODING_READ_ADDRESS => CODING_READ_ADDRESS,
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CODING_WRITE_ADDRESS => CODING_WRITE_ADDRESS,
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CLK => CLK,
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CLEAR => CLEAR,
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ENABLE_WRITE => ENABLE_WRITE_INT,
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ENABLE_READ => ENABLE_READ_INT,
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ENABLE_PARSER => READY_AUX, -- data for the parser ready
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CLEAR_COUNTERS => CLEAR_COUNTERS,
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RESET_TOTAL_COUNTER => RESET_TOTAL_COUNTER,
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BUS_REQUEST => BUS_REQUEST_INT
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);
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READ_COUNTER : INPUT_COUNTER
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port map(ENABLE => ENABLE_READ,
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CLEAR => CLEAR,
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CLEAR_COUNTERS => CLEAR_COUNTERS,
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CLK => CLK,
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COUNT => CODING_READ_ADDRESS
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);
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WRITE_COUNTER : INPUT_COUNTER
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port map(ENABLE => ENABLE_WRITE_WITH_WAIT,
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CLEAR =>CLEAR,
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CLEAR_COUNTERS => CLEAR_COUNTERS,
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CLK => CLK,
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COUNT => CODING_WRITE_ADDRESS
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);
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ENABLE_WRITE_WITH_WAIT <= ENABLE_WRITE and WAITN;
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-- xilinx memory
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RAM_SB: DP_RAM_XILINX_256
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port map(
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addra => WRADDRESS_SB,
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clka => WRCLOCK_SB,
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addrb => RDADDRESS_SB,
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clkb => RDCLOCK_SB,
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dina => DATA_SB,
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wea(0) => WREN_SB,
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enb => RDEN_SB,
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doutb => DATA_OUT_AUX(31 downto 0));
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-- Actel memory
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--RAM_SB : MY_MEMORY
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--port map(DO => DATA_OUT_AUX(31 downto 0),
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-- RCLOCK =>RDCLOCK_SB,
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-- WCLOCK =>WRCLOCK_SB,
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-- DI => DATA_SB,
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-- WRB => WREN_SB,
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-- RDB =>RDEN_SB,
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-- WADDR => WRADDRESS_SB,
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-- RADDR => RDADDRESS_SB
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--);
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-- Altera memory
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-- Altera memory
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-- pragma translate off
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--ALT_RAM :
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--
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--if (not TSMC013) generate
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--
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--RAM_SB: LPM_RAM_DP
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--generic map(LPM_WIDTH => 32,
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-- LPM_WIDTHAD => 8,
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-- LPM_NUMWORDS => 256,
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-- LPM_INDATA => "REGISTERED",
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-- LPM_OUTDATA => "UNREGISTERED",
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-- LPM_RDADDRESS_CONTROL => "REGISTERED",
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-- LPM_WRADDRESS_CONTROL => "REGISTERED",
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-- LPM_FILE => "UNUSED",
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-- LPM_TYPE => "LPM_RAM_DP",
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-- LPM_HINT => "UNUSED")
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--port map(
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-- DATA=> DATA_SB,
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-- RDADDRESS=> RDADDRESS_SB,
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-- WRADDRESS=> WRADDRESS_SB,
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-- RDEN=> RDEN_SB,
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-- WREN=> WREN_SB,
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-- Q=> DATA_OUT_AUX(31 downto 0),
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-- RDCLOCK=> RDCLOCK_SB,
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-- RDCLKEN=> RDCLKEN_SB,
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-- WRCLOCK=> WRCLOCK_SB,
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-- WRCLKEN=> WRCLKEN_SB
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--);
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--
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--end generate;
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--pragma translate on
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-- Port 1 = R
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-- Port 2 = R/W
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--TSMC013_RAM :
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--
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361 |
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-- if (TSMC013) generate
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362 |
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-- TMSC_RAM : ra2sh_256W_32B_8MX_offWRMSK_8WRGRAN port map
|
363 |
|
|
-- (
|
364 |
|
|
-- clka => RDCLOCK_SB,
|
365 |
|
|
-- cena => tsmc_cena_n ,
|
366 |
|
|
-- wena => tsmc_wena_n,
|
367 |
|
|
-- aa => RDADDRESS_SB,
|
368 |
|
|
-- da => DATA_SB,
|
369 |
|
|
-- qa => DATA_OUT_AUX,
|
370 |
|
|
-- clkb => WRCLOCK_SB,
|
371 |
|
|
-- cenb => tsmc_cenb_n,
|
372 |
|
|
-- wenb => tsmc_wenb_n,
|
373 |
|
|
-- ab => WRADDRESS_SB,
|
374 |
|
|
-- db => DATA_SB,
|
375 |
|
|
-- qb => OPEN
|
376 |
|
|
-- ) ;
|
377 |
|
|
--
|
378 |
|
|
-- end generate;
|
379 |
|
|
|
380 |
|
|
tsmc_cenb_n <= not (WRCLKEN_SB);
|
381 |
|
|
|
382 |
|
|
tsmc_cena_n <= not (RDCLKEN_SB);
|
383 |
|
|
|
384 |
|
|
tsmc_wena_n <='1';
|
385 |
|
|
|
386 |
|
|
-- not (RDEN_SB); Always in read-mode; read-enable used to
|
387 |
|
|
|
388 |
|
|
-- power-up ram
|
389 |
|
|
|
390 |
|
|
tsmc_wenb_n <= not (WREN_SB);
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
DATA_SB<=To_X01Z(DATA_IN_32) after 5 ns;
|
394 |
|
|
RDADDRESS_SB<= To_X01Z(CODING_READ_ADDRESS) after 5 ns;
|
395 |
|
|
WRADDRESS_SB<= To_X01Z(CODING_WRITE_ADDRESS) after 5 ns;
|
396 |
|
|
RDEN_SB<= To_X01Z(ENABLE_READ) after 5 ns;
|
397 |
|
|
WREN_SB<= To_X01Z(ENABLE_WRITE) after 5 ns;
|
398 |
|
|
RDCLOCK_SB<= To_X01Z(READ_CLK);
|
399 |
|
|
RDCLKEN_SB<= To_X01Z(READ_CLK_ENABLE) after 5 ns;
|
400 |
|
|
WRCLOCK_SB<= To_X01Z(WRITE_CLK);
|
401 |
|
|
WRCLKEN_SB<= To_X01Z(WRITE_CLK_ENABLE) after 5 ns;
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
DATA_OUT_32 <= To_bitvector(DATA_OUT_AUX);-- when ENABLE_READ_INT = '1' else x"00000000";
|
405 |
|
|
WRITE_CLK <= CLK;
|
406 |
|
|
READ_CLK <= CLK;
|
407 |
|
|
ENABLE_READ <= (ENABLE_READ_INT and READ);
|
408 |
|
|
ENABLE_WRITE <= ENABLE_WRITE_INT;
|
409 |
|
|
WRITE_CLK_ENABLE <= ENABLE_WRITE_INT;
|
410 |
|
|
READ_CLK_ENABLE <= ENABLE_READ_INT;
|
411 |
|
|
BUS_REQUEST <= BUS_REQUEST_INT;
|
412 |
|
|
READY <=READY_AUX;
|
413 |
|
|
|
414 |
|
|
INC_TC <= ENABLE_WRITE_WITH_WAIT;
|
415 |
|
|
|
416 |
|
|
end STRUCTURAL;
|