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eejlny |
--This library is free software; you can redistribute it and/or
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--modify it under the terms of the GNU Lesser General Public
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--License as published by the Free Software Foundation; either
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--version 2.1 of the License, or (at your option) any later version.
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--This library is distributed in the hope that it will be useful,
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--but WITHOUT ANY WARRANTY; without even the implied warranty of
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--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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--Lesser General Public License for more details.
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--You should have received a copy of the GNU Lesser General Public
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--License along with this library; if not, write to the Free Software
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--Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- e_mail : j.l.nunez-yanez@byacom.co.uk
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--------------------------------------
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-- ENTITY = LEVEL2_4 --
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-- version = 1.0 --
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-- last update = 1/08/99 --
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-- author = Jose Nunez --
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--------------------------------------
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-- FUNCTION
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-- hierarchy level.
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-- PIN LIST
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-- COMP_INT = selects compression mode
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-- DECOMP_INT = selects decompression mode
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-- MOVE_ENABLE = activates the movement in the dictionary
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-- CLK = master clock
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-- CLEAR = asynchronous reset
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-- U_DATAIN = data to be compressed
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-- C_DATAIN = data to be decompressed
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-- U_DATAOUT = decompressed data
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-- C_DATAOUT = compressed data
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-- FLUSH_INT = activate flush cycle
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-- FLUSH_END = internal flush terminated
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-- ADDRESS = memory address signal
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-- CE = memory chip enable
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-- OE = memory output enable
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-- RW = memory read or write enable
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library IEEE;
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use IEEE.std_logic_1164.all;
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--------------------------------------
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-- ENTITY = CG_ASSEMBLY --
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-- version = 1.0 --
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-- last update = 1/08/98 --
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-- author = Jose Nunez --
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--------------------------------------
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-- FUNCTION
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-- hierarchy level that includes all the assembly logic for compression.
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-- PIN LIST
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-- SEARCH_STRING : literals
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-- MATCH_TYPE : match type of best match
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-- MATCH_LOC : match location of best match (coded)
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-- CLEAR : asyncronus clear
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-- CLK : master clk
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-- MISS : miss detection
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-- FLUSH : pipeline activate flush cycle signal from csm
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-- OVERFLOW : overflow detection data ready to be output
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-- DOUT : 64 bits of compressed data
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-- FLUSH_END : end of flush cycle
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-- COMP : activate compression mode
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entity CG_ASSEMBLY is
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port(
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RL_DETECTED : in bit;
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COUNT_IN : in bit_vector(7 downto 0);
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NFL_M_ONE : in bit_vector(3 downto 0);
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TABLE_FULL : in bit;
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SEARCH_STRING : in bit_vector(31 downto 0);
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MASK : in bit_vector(4 downto 0);
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MATCH_TYPE : in bit_vector(3 downto 0);
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MATCH_LOC : in bit_vector(3 downto 0);
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CLEAR : in bit;
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RESET : in bit;
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CLK : in bit;
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FLUSH : in bit;
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FLUSH_RLI : in bit;
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OVERFLOW : out bit;
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SHORT : out bit;
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DOUT : out bit_vector(97 downto 34);
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FLUSH_END : out bit;
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MOVE_ENABLE : in bit;
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COMP : in bit
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);
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end CG_ASSEMBLY;
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architecture CG_ASSEMBLY of CG_ASSEMBLY is
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-- Component declarations
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component MT_CODER
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port(
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MATCH_TYPE : in bit_vector(3 downto 0);
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CODE : out bit_vector(5 downto 0);
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LENGTH : out bit_vector(2 downto 0)
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);
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end component;
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--change
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component CM_ASSEMBLER
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port(
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CODE_A : in bit_vector(4 downto 0);
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LENGTH_A : in bit_vector(2 downto 0);
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MISS : in bit;
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CODE_B : in bit_vector(5 downto 0);
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LENGTH_B : in bit_vector(2 downto 0);
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CODE_OUT : out bit_vector(10 downto 0);
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LENGTH_OUT : out bit_vector(3 downto 0)
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);
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end component;
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component LC_ASSEMBLER
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port(
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MASK : in bit_vector(4 downto 0);
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MATCH_TYPE : in bit_vector(3 downto 0);
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LITERAL_DATA : in bit_vector(31 downto 0);
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MISS : out bit;
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CODE : out bit_vector(33 downto 0);
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LENGTH : out bit_vector(5 downto 0)
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);
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end component;
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component CML_ASSEMBLER
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port(
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CODE_A : in bit_vector(10 downto 0);
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LENGTH_A : in bit_vector(3 downto 0);
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CODE_B : in bit_vector(33 downto 0);
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LENGTH_B : in bit_vector(5 downto 0);
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CODE_OUT : out bit_vector(34 downto 0);
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LENGTH_OUT : out bit_vector(5 downto 0)
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);
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end component;
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component LATCH98
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port(
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D_IN : in bit_vector(97 downto 0);
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CLEAR : in bit;
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RESET : in bit;
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CLK : in bit;
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D_OUT : out bit_vector(97 downto 0)
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);
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end component;
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component LATCH6
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port(
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D_IN : in bit_vector(5 downto 0);
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CLEAR : in bit;
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RESET : in bit;
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CLK : in bit;
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D_OUT : out bit_vector(5 downto 0)
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);
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end component;
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component RLI_coding_logic
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port
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(
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RL_DETECTED : in bit;
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COUNT_IN : in bit_vector(7 downto 0);
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MOVE_ENABLE_IN : in bit;
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COMP_IN : in bit;
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FLUSH_IN: in bit;
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FLUSH_RLI : in bit;
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CODE_IN : in bit_vector(34 downto 0);
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LENGTH_IN : in bit_vector(5 downto 0);
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CODE_RLI : in bit_vector(4 downto 0);
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CODE_RLI_LENGTH : in bit_vector(2 downto 0);
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CLEAR : in bit;
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RESET : in bit;
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CLK : in bit;
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FLUSH_OUT: out bit;
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COMP_OUT: out bit;
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CODE_OUT : out bit_vector(34 downto 0);
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LENGTH_OUT : out bit_vector(5 downto 0)
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);
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end component;
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component PIPELINE_R4
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port (
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FLUSH_IN : in bit;
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CODE_IN : in bit_vector (34 downto 0);
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LENGTH_IN : in bit_vector (5 downto 0);
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COMP_IN :in bit;
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CLEAR:in bit;
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CLK :in bit;
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FLUSH_OUT:out bit;
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CODE_OUT:out bit_vector(34 downto 0);
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LENGTH_OUT:out bit_vector( 5 downto 0);
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COMP_OUT: out bit
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);
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end component;
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component OB_ASSEMBLER
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port(
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CODE_OLD : in bit_vector(97 downto 0);
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LENGTH_OLD : in bit_vector(5 downto 0);
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COMP : in bit;
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FLUSH_IN : in bit;
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CODE_IN : in bit_vector(34 downto 0);
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LENGTH_IN : in bit_vector(5 downto 0);
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CODE_NEW : out bit_vector(97 downto 0);
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LENGTH_NEW : out bit_vector(5 downto 0);
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OVERFLOW_LENGTH : out bit;
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FLUSH_END : out bit;
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OVERFLOW_OLD : in bit;
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CLEAR : in bit;
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RESET : in bit;
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CLK : in bit;
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SHORT : out bit;
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OVERFLOW_FLUSH : out bit
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);
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end component;
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component OV_LATCH
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port(
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CLEAR : in bit;
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RESET : in bit;
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CLK : in bit;
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OVERFLOW_LENGTH : in bit;
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OVERFLOW_FLUSH : in bit;
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OVERFLOW_MEM : out bit;
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OVERFLOW_OLD : out bit
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);
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end component;
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component PC_GENERATE
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port
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(
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NFL_M_ONE : in bit_vector(3 downto 0);
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MATCH_LOC : in bit_vector(3 downto 0);
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MISS : in bit;
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TABLE_FULL : in bit;
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CODE : out bit_vector(4 downto 0);
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LENGTH : out bit_vector(2 downto 0)
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);
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end component;
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-- Signal declarations
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signal FLUSH_INT_2:bit;
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signal FLUSH_RL:bit;
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signal MISS : bit;
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signal COMP_RL:bit;
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signal COMP_INT_2 : bit;
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signal CODE_IN_INT: bit_vector(34 downto 0);
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signal CODE_IN : bit_vector(34 downto 0);
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signal CODE_IN_RL : bit_vector(34 downto 0);
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signal LENGTH_IN : bit_vector(5 downto 0);
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signal LENGTH_IN_RL : bit_vector(5 downto 0);
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signal LENGTH_IN_INT : bit_vector(5 downto 0);
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signal LIT_CODE : bit_vector(33 downto 0);
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signal LIT_LENGTH : bit_vector(5 downto 0);
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signal M_T_CODE : bit_vector(10 downto 0);
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signal M_T_LENGTH : bit_vector(3 downto 0);
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signal MATCH_CODE : bit_vector(4 downto 0);
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signal MATCH_LENGTH : bit_vector(2 downto 0);
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signal NEW_CODE : bit_vector(97 downto 0);
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signal NEW_LENGTH : bit_vector(5 downto 0);
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signal OLD_CODE : bit_vector(97 downto 0);
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signal OLD_LENGTH : bit_vector(5 downto 0);
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signal OVERFLOW_FLUSH : bit;
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signal OVERFLOW_LENGTH : bit;
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signal OVERFLOW_OLD : bit;
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signal SEARCH : bit_vector(31 downto 0);
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signal TYPE_CODE : bit_vector(5 downto 0);
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signal TYPE_LENGTH : bit_vector(2 downto 0);
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274 |
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begin
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-- Signal assignments
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277 |
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SEARCH <= SEARCH_STRING;
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DOUT(97 downto 34) <= OLD_CODE(97 downto 34);
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279 |
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280 |
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-- Component instances
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281 |
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MT_CODER_1 : MT_CODER
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port map(
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MATCH_TYPE => MATCH_TYPE,
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284 |
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CODE => TYPE_CODE,
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285 |
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LENGTH => TYPE_LENGTH
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);
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287 |
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CM_ASSEMBLER_1 : CM_ASSEMBLER
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288 |
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port map(
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289 |
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CODE_A => MATCH_CODE,
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LENGTH_A => MATCH_LENGTH,
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MISS => MISS,
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292 |
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CODE_B => TYPE_CODE,
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293 |
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LENGTH_B => TYPE_LENGTH,
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294 |
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CODE_OUT => M_T_CODE,
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295 |
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LENGTH_OUT => M_T_LENGTH
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);
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297 |
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298 |
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LC_ASSEMBLER_1 : LC_ASSEMBLER
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299 |
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port map(
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300 |
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MATCH_TYPE => MATCH_TYPE,
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301 |
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MASK => MASK,
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302 |
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LITERAL_DATA => SEARCH,
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303 |
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MISS => MISS,
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304 |
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CODE => LIT_CODE,
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305 |
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LENGTH => LIT_LENGTH
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306 |
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);
|
307 |
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308 |
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309 |
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CML_ASSEMBLER_1 : CML_ASSEMBLER
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310 |
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port map(
|
311 |
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CODE_A => M_T_CODE,
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312 |
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LENGTH_A => M_T_LENGTH,
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313 |
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CODE_B => LIT_CODE,
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314 |
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LENGTH_B => LIT_LENGTH,
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315 |
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CODE_OUT => CODE_IN,
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316 |
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LENGTH_OUT => LENGTH_IN
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317 |
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);
|
318 |
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LATCH98_1 : LATCH98
|
319 |
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port map(
|
320 |
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D_IN => NEW_CODE,
|
321 |
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RESET => RESET,
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322 |
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CLEAR => CLEAR,
|
323 |
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CLK => CLK,
|
324 |
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D_OUT => OLD_CODE
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325 |
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);
|
326 |
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LATCH6_1 : LATCH6
|
327 |
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port map(
|
328 |
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D_IN => NEW_LENGTH,
|
329 |
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CLEAR => CLEAR,
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330 |
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RESET => RESET,
|
331 |
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CLK => CLK,
|
332 |
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D_OUT => OLD_LENGTH
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333 |
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);
|
334 |
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|
335 |
|
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RLI_CL : RLI_coding_logic
|
336 |
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port map
|
337 |
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(
|
338 |
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RL_DETECTED => RL_DETECTED,
|
339 |
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COUNT_IN => COUNT_IN,
|
340 |
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COMP_IN => COMP,
|
341 |
|
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MOVE_ENABLE_IN => MOVE_ENABLE,
|
342 |
|
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FLUSH_IN => FLUSH,
|
343 |
|
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FLUSH_RLI => FLUSH_RLI,
|
344 |
|
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CODE_IN => CODE_IN,
|
345 |
|
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LENGTH_IN => LENGTH_IN,
|
346 |
|
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CODE_RLI => MATCH_CODE,
|
347 |
|
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CODE_RLI_LENGTH => MATCH_LENGTH,
|
348 |
|
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CLEAR => CLEAR,
|
349 |
|
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RESET=>RESET,
|
350 |
|
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CLK => CLK,
|
351 |
|
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FLUSH_OUT => FLUSH_RL,
|
352 |
|
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COMP_OUT => COMP_RL,
|
353 |
|
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CODE_OUT => CODE_IN_RL,
|
354 |
|
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LENGTH_OUT => LENGTH_IN_RL
|
355 |
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);
|
356 |
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|
357 |
|
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|
358 |
|
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PIPELINE_R4_4 : PIPELINE_R4
|
359 |
|
|
port map(
|
360 |
|
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FLUSH_IN => FLUSH_RL,
|
361 |
|
|
CODE_IN => CODE_IN_RL,
|
362 |
|
|
LENGTH_IN => LENGTH_IN_RL,
|
363 |
|
|
COMP_IN => COMP_RL,
|
364 |
|
|
CLEAR => CLEAR,
|
365 |
|
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CLK => CLK,
|
366 |
|
|
FLUSH_OUT => FLUSH_INT_2,
|
367 |
|
|
CODE_OUT => CODE_IN_INT,
|
368 |
|
|
LENGTH_OUT => LENGTH_IN_INT,
|
369 |
|
|
COMP_OUT => COMP_INT_2
|
370 |
|
|
);
|
371 |
|
|
|
372 |
|
|
OB_ASSEMBLER_1 : OB_ASSEMBLER
|
373 |
|
|
port map(
|
374 |
|
|
CODE_OLD => OLD_CODE,
|
375 |
|
|
LENGTH_OLD => OLD_LENGTH,
|
376 |
|
|
COMP => COMP_INT_2,
|
377 |
|
|
FLUSH_IN => FLUSH_INT_2,
|
378 |
|
|
CODE_IN => CODE_IN_INT,
|
379 |
|
|
LENGTH_IN => LENGTH_IN_INT,
|
380 |
|
|
CODE_NEW => NEW_CODE,
|
381 |
|
|
LENGTH_NEW => NEW_LENGTH,
|
382 |
|
|
OVERFLOW_LENGTH => OVERFLOW_LENGTH,
|
383 |
|
|
FLUSH_END => FLUSH_END,
|
384 |
|
|
OVERFLOW_OLD => OVERFLOW_OLD,
|
385 |
|
|
CLEAR => CLEAR,
|
386 |
|
|
RESET => RESET,
|
387 |
|
|
CLK => CLK,
|
388 |
|
|
SHORT => SHORT,
|
389 |
|
|
OVERFLOW_FLUSH => OVERFLOW_FLUSH
|
390 |
|
|
);
|
391 |
|
|
OV_LATCH_1 : OV_LATCH
|
392 |
|
|
port map(
|
393 |
|
|
RESET => RESET,
|
394 |
|
|
CLEAR => CLEAR,
|
395 |
|
|
CLK => CLK,
|
396 |
|
|
OVERFLOW_LENGTH => OVERFLOW_LENGTH,
|
397 |
|
|
OVERFLOW_FLUSH => OVERFLOW_FLUSH,
|
398 |
|
|
OVERFLOW_MEM => OVERFLOW,
|
399 |
|
|
OVERFLOW_OLD => OVERFLOW_OLD
|
400 |
|
|
);
|
401 |
|
|
|
402 |
|
|
PC_GENERATE_1 : PC_GENERATE
|
403 |
|
|
port map(
|
404 |
|
|
NFL_M_ONE => NFL_M_ONE,
|
405 |
|
|
MATCH_LOC => MATCH_LOC,
|
406 |
|
|
MISS =>MISS,
|
407 |
|
|
TABLE_FULL => TABLE_FULL,
|
408 |
|
|
CODE =>MATCH_CODE,
|
409 |
|
|
LENGTH => MATCH_LENGTH
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
end CG_ASSEMBLY;
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
library IEEE;
|
417 |
|
|
use IEEE.std_logic_1164.all;
|
418 |
|
|
|
419 |
|
|
entity level2_4ca is
|
420 |
|
|
port(
|
421 |
|
|
CLK : in bit;
|
422 |
|
|
RESET : in bit;
|
423 |
|
|
CLEAR : in bit;
|
424 |
|
|
COMP : in bit;
|
425 |
|
|
MOVE_ENABLE : in bit;
|
426 |
|
|
FLUSH : in bit;
|
427 |
|
|
U_DATAIN : in bit_vector(31 downto 0);
|
428 |
|
|
MASK : in bit_vector(4 downto 0);
|
429 |
|
|
FLUSH_END : out bit ;
|
430 |
|
|
C_DATAOUT : out bit_vector(63 downto 0);
|
431 |
|
|
SHORT : out bit;
|
432 |
|
|
OVERFLOW : out bit
|
433 |
|
|
);
|
434 |
|
|
end level2_4ca;
|
435 |
|
|
|
436 |
|
|
architecture level2_4ca of level2_4ca is
|
437 |
|
|
-- Component declarations
|
438 |
|
|
component SREG
|
439 |
|
|
port(
|
440 |
|
|
DIN : in bit_vector(31 downto 0);
|
441 |
|
|
MASK_IN : in bit_vector(4 downto 0);
|
442 |
|
|
CLEAR : in bit;
|
443 |
|
|
CLK : in bit;
|
444 |
|
|
MASK_OUT : out bit_vector(4 downto 0);
|
445 |
|
|
QOUT : out bit_vector(31 downto 0)
|
446 |
|
|
);
|
447 |
|
|
end component;
|
448 |
|
|
|
449 |
|
|
component PIPELINE_R0
|
450 |
|
|
port(
|
451 |
|
|
DOWN_PRIORITY_6_IN : in bit_vector(15 downto 0);
|
452 |
|
|
DOWN_PRIORITY_5_IN : in bit_vector(15 downto 0);
|
453 |
|
|
DOWN_PRIORITY_4_IN : in bit_vector(15 downto 0);
|
454 |
|
|
DOWN_PRIORITY_3_IN : in bit_vector(15 downto 0);
|
455 |
|
|
DOWN_PRIORITY_2_IN : in bit_vector(15 downto 0);
|
456 |
|
|
DOWN_PRIORITY_1_IN : in bit_vector(15 downto 0);
|
457 |
|
|
SAME_LENGTH_IN_2 : in bit_vector(15 downto 0);
|
458 |
|
|
SAME_LENGTH_IN_3 : in bit_vector(15 downto 0);
|
459 |
|
|
SAME_LENGTH_IN_4 : in bit_vector(15 downto 0);
|
460 |
|
|
MATCH_TYPE_A_IN : in bit_vector(15 downto 0);
|
461 |
|
|
MATCH_TYPE_B_IN : in bit_vector(15 downto 0);
|
462 |
|
|
MATCH_TYPE_C_IN : in bit_vector(15 downto 0);
|
463 |
|
|
MATCH_TYPE_D_IN : in bit_vector(15 downto 0);
|
464 |
|
|
SEARCH_STRING_IN : in bit_vector(31 downto 0);
|
465 |
|
|
MASK_IN : in bit_vector(4 downto 0);
|
466 |
|
|
COLUMN_OR_IN : in bit_vector(6 downto 1);
|
467 |
|
|
FLUSH_IN : in bit;
|
468 |
|
|
COMP_IN : in bit;
|
469 |
|
|
MOVE_ENABLE_IN : in bit;
|
470 |
|
|
INC_CAM_IN : in bit;
|
471 |
|
|
CLK : in bit;
|
472 |
|
|
CLEAR : in bit;
|
473 |
|
|
RESET : in bit;
|
474 |
|
|
DOWN_PRIORITY_6_OUT : out bit_vector(15 downto 0);
|
475 |
|
|
DOWN_PRIORITY_5_OUT : out bit_vector(15 downto 0);
|
476 |
|
|
DOWN_PRIORITY_4_OUT : out bit_vector(15 downto 0);
|
477 |
|
|
DOWN_PRIORITY_3_OUT : out bit_vector(15 downto 0);
|
478 |
|
|
DOWN_PRIORITY_2_OUT : out bit_vector(15 downto 0);
|
479 |
|
|
DOWN_PRIORITY_1_OUT : out bit_vector(15 downto 0);
|
480 |
|
|
SAME_LENGTH_OUT_2 : out bit_vector(15 downto 0);
|
481 |
|
|
SAME_LENGTH_OUT_3 : out bit_vector(15 downto 0);
|
482 |
|
|
SAME_LENGTH_OUT_4 : out bit_vector(15 downto 0);
|
483 |
|
|
MATCH_TYPE_A_OUT : out bit_vector(15 downto 0);
|
484 |
|
|
MATCH_TYPE_B_OUT : out bit_vector(15 downto 0);
|
485 |
|
|
MATCH_TYPE_C_OUT : out bit_vector(15 downto 0);
|
486 |
|
|
MATCH_TYPE_D_OUT : out bit_vector(15 downto 0);
|
487 |
|
|
SEARCH_STRING_OUT : out bit_vector(31 downto 0);
|
488 |
|
|
MASK_OUT : out bit_vector(4 downto 0);
|
489 |
|
|
COLUMN_OR_OUT : out bit_vector(6 downto 1);
|
490 |
|
|
FLUSH_OUT : out bit;
|
491 |
|
|
COMP_OUT : out bit;
|
492 |
|
|
MOVE_ENABLE_OUT : out bit;
|
493 |
|
|
INC_CAM_OUT : out bit
|
494 |
|
|
);
|
495 |
|
|
end component;
|
496 |
|
|
|
497 |
|
|
component MLD_LOGIC_3_1_2
|
498 |
|
|
port(
|
499 |
|
|
TYPE_A : in bit_vector(15 downto 0) ;
|
500 |
|
|
TYPE_B : in bit_vector(15 downto 0) ;
|
501 |
|
|
TYPE_C : in bit_vector(15 downto 0) ;
|
502 |
|
|
TYPE_D : in bit_vector(15 downto 0) ;
|
503 |
|
|
DOWN_PRIORITY_6 : out bit_vector(15 downto 0);
|
504 |
|
|
DOWN_PRIORITY_5 : out bit_vector(15 downto 0);
|
505 |
|
|
DOWN_PRIORITY_4 : out bit_vector(15 downto 0);
|
506 |
|
|
DOWN_PRIORITY_3 : out bit_vector(15 downto 0);
|
507 |
|
|
DOWN_PRIORITY_2 : out bit_vector(15 downto 0);
|
508 |
|
|
DOWN_PRIORITY_1 : out bit_vector(15 downto 0);
|
509 |
|
|
COLUMN_OR : out bit_vector(6 downto 1)
|
510 |
|
|
);
|
511 |
|
|
end component;
|
512 |
|
|
component MLD_LOGIC_3_2_2
|
513 |
|
|
port(
|
514 |
|
|
MASK : in bit_vector(4 downto 0);
|
515 |
|
|
DOWN_PRIORITY_6 : in bit_vector(15 downto 0) ;
|
516 |
|
|
DOWN_PRIORITY_5 : in bit_vector(15 downto 0) ;
|
517 |
|
|
DOWN_PRIORITY_4 : in bit_vector(15 downto 0) ;
|
518 |
|
|
DOWN_PRIORITY_3 : in bit_vector(15 downto 0) ;
|
519 |
|
|
DOWN_PRIORITY_2 : in bit_vector(15 downto 0) ;
|
520 |
|
|
DOWN_PRIORITY_1 : in bit_vector(15 downto 0) ;
|
521 |
|
|
SAME_LENGTH_2 : in bit_vector(15 downto 0);
|
522 |
|
|
SAME_LENGTH_3 : in bit_vector(15 downto 0);
|
523 |
|
|
SAME_LENGTH_4 : in bit_vector(15 downto 0);
|
524 |
|
|
MATCH_TYPE_A : in bit_vector(15 downto 0);
|
525 |
|
|
MATCH_TYPE_B : in bit_vector(15 downto 0);
|
526 |
|
|
MATCH_TYPE_C : in bit_vector(15 downto 0);
|
527 |
|
|
MATCH_TYPE_D : in bit_vector(15 downto 0);
|
528 |
|
|
COLUMN_OR : in bit_vector(6 downto 1);
|
529 |
|
|
MATCH_LOC : out bit_vector(15 downto 0) ;
|
530 |
|
|
MATCH_TYPE : out bit_vector(3 downto 0)
|
531 |
|
|
);
|
532 |
|
|
end component;
|
533 |
|
|
|
534 |
|
|
|
535 |
|
|
component MC_MUX_3C
|
536 |
|
|
port(
|
537 |
|
|
A : in bit_vector(15 downto 0);
|
538 |
|
|
ENABLEC: in bit;
|
539 |
|
|
Y : out bit_vector(15 downto 0)
|
540 |
|
|
);
|
541 |
|
|
end component;
|
542 |
|
|
|
543 |
|
|
component CAM_ARRAY_ZERO
|
544 |
|
|
port(
|
545 |
|
|
SEARCH_DATA : in bit_vector(31 downto 0);
|
546 |
|
|
SEARCH_MASK : in bit_vector(3 downto 0);
|
547 |
|
|
PREVIOUS_DATA : in bit_vector(31 downto 0);
|
548 |
|
|
PREVIOUS_MASK : in bit_vector(3 downto 0);
|
549 |
|
|
ENABLE : in bit; -- do not load tuple 0 when waiting for data from the buffer
|
550 |
|
|
MOVE : in bit_vector(15 downto 1);
|
551 |
|
|
CLEAR : in bit;
|
552 |
|
|
RESET : in bit;
|
553 |
|
|
CLK : in bit;
|
554 |
|
|
SAME_LENGTH_2 : out bit_vector(15 downto 0);
|
555 |
|
|
SAME_LENGTH_3 : out bit_vector(15 downto 0);
|
556 |
|
|
SAME_LENGTH_4 : out bit_vector(15 downto 0);
|
557 |
|
|
MTYPE_A : out bit_vector(15 downto 0);
|
558 |
|
|
MTYPE_B : out bit_vector(15 downto 0);
|
559 |
|
|
MTYPE_C : out bit_vector(15 downto 0);
|
560 |
|
|
MTYPE_D : out bit_vector(15 downto 0)
|
561 |
|
|
);
|
562 |
|
|
end component;
|
563 |
|
|
|
564 |
|
|
component PIPELINE_R1
|
565 |
|
|
|
566 |
|
|
port(
|
567 |
|
|
|
568 |
|
|
MATCH_LOC_IN: in bit_vector( 15 downto 0);
|
569 |
|
|
MATCH_TYPE_IN: in bit_vector(3 downto 0);
|
570 |
|
|
SEARCH_STRING_IN: in bit_vector(31 downto 0);
|
571 |
|
|
MASK_IN : in bit_vector(4 downto 0);
|
572 |
|
|
FLUSH_IN:in bit;
|
573 |
|
|
COMP_IN:in bit;
|
574 |
|
|
MOVE_ENABLE_IN : in bit;
|
575 |
|
|
INC_IN: in bit;
|
576 |
|
|
CLEAR:in bit;
|
577 |
|
|
RESET: in bit;
|
578 |
|
|
CLK:in bit;
|
579 |
|
|
MATCH_LOC_OUT: out bit_vector (15 downto 0);
|
580 |
|
|
MATCH_TYPE_OUT:out bit_vector(3 downto 0);
|
581 |
|
|
SEARCH_STRING_OUT: out bit_vector(31 downto 0);
|
582 |
|
|
MASK_OUT : out bit_vector(4 downto 0);
|
583 |
|
|
FLUSH_OUT:out bit;
|
584 |
|
|
COMP_OUT:out bit;
|
585 |
|
|
MOVE_ENABLE_OUT : out bit;
|
586 |
|
|
INC_OUT:out bit
|
587 |
|
|
);
|
588 |
|
|
end component;
|
589 |
|
|
|
590 |
|
|
component ENCODE16_4
|
591 |
|
|
port(
|
592 |
|
|
MATCH_LOC_IN : in bit_vector(15 downto 0);
|
593 |
|
|
MATCH_LOC_OUT : out bit_vector(3 downto 0)
|
594 |
|
|
|
595 |
|
|
);
|
596 |
|
|
end component;
|
597 |
|
|
|
598 |
|
|
component NFL_COUNTERS2
|
599 |
|
|
port(
|
600 |
|
|
INC : in bit ;
|
601 |
|
|
COUNT_ENABLE : in bit ;
|
602 |
|
|
CLK : in bit ;
|
603 |
|
|
RESET : in bit ;
|
604 |
|
|
CLEAR : in bit;
|
605 |
|
|
NFL_MINUS_ONE : out bit_vector(7 downto 0) ;
|
606 |
|
|
TABLE_FULL : out bit
|
607 |
|
|
);
|
608 |
|
|
end component;
|
609 |
|
|
|
610 |
|
|
|
611 |
|
|
|
612 |
|
|
component RLI_COUNTER_C
|
613 |
|
|
port (
|
614 |
|
|
MOVE_ENABLE : in bit;
|
615 |
|
|
ENABLE_C : in bit;
|
616 |
|
|
LOCATION_ZERO : in bit;
|
617 |
|
|
SAME_POSITION : in bit;
|
618 |
|
|
CLEAR : in bit;
|
619 |
|
|
RESET : in bit;
|
620 |
|
|
CLK : in bit;
|
621 |
|
|
COUNT : out bit_vector(7 downto 0);
|
622 |
|
|
RL_DETECTED : out bit
|
623 |
|
|
);
|
624 |
|
|
end component;
|
625 |
|
|
|
626 |
|
|
component COUNT_DELAY
|
627 |
|
|
port(
|
628 |
|
|
COUNT_IN : in bit_vector(7 downto 0);
|
629 |
|
|
CLEAR: in bit;
|
630 |
|
|
RESET : in bit;
|
631 |
|
|
CLK : in bit;
|
632 |
|
|
COUNT_OUT :out bit_vector(7 downto 0)
|
633 |
|
|
|
634 |
|
|
);
|
635 |
|
|
end component;
|
636 |
|
|
|
637 |
|
|
component FULL_MATCH_D
|
638 |
|
|
|
639 |
|
|
port (
|
640 |
|
|
NFL_M_ONE : in bit_vector(7 downto 0);
|
641 |
|
|
MOVE_ENABLE : in bit;
|
642 |
|
|
PRIORITY_6: in bit_vector(15 downto 0);
|
643 |
|
|
PRIORITY_5: in bit_vector(15 downto 0);
|
644 |
|
|
PRIORITY_2: in bit_vector(15 downto 0);
|
645 |
|
|
SAME_LENGTH_2: in bit_vector(15 downto 0);
|
646 |
|
|
SAME_LENGTH_3: in bit_vector(15 downto 0);
|
647 |
|
|
SAME_LENGTH_4: in bit_vector(15 downto 0);
|
648 |
|
|
CLK : in bit;
|
649 |
|
|
CLEAR : in bit;
|
650 |
|
|
RESET : in bit;
|
651 |
|
|
FULL_MATCH : out bit;
|
652 |
|
|
FULL_MATCH_AT_ZERO : out bit;
|
653 |
|
|
SAME_POSITION : out bit;
|
654 |
|
|
FULL_MATCH_VECTOR : out bit_vector(15 downto 0)
|
655 |
|
|
);
|
656 |
|
|
end component;
|
657 |
|
|
|
658 |
|
|
component CG_ASSEMBLY
|
659 |
|
|
port(
|
660 |
|
|
RL_DETECTED : in bit;
|
661 |
|
|
COUNT_IN : in bit_vector(7 downto 0);
|
662 |
|
|
NFL_M_ONE : in bit_vector(3 downto 0);
|
663 |
|
|
TABLE_FULL : in bit;
|
664 |
|
|
SEARCH_STRING : in bit_vector(31 downto 0);
|
665 |
|
|
MASK : in bit_vector(4 downto 0);
|
666 |
|
|
MATCH_TYPE : in bit_vector(3 downto 0);
|
667 |
|
|
MATCH_LOC : in bit_vector(3 downto 0);
|
668 |
|
|
CLEAR : in bit;
|
669 |
|
|
RESET : in bit;
|
670 |
|
|
CLK : in bit;
|
671 |
|
|
FLUSH : in bit;
|
672 |
|
|
FLUSH_RLI : in bit;
|
673 |
|
|
OVERFLOW : out bit;
|
674 |
|
|
SHORT : out bit;
|
675 |
|
|
DOUT : out bit_vector(95 downto 32);
|
676 |
|
|
FLUSH_END : out bit;
|
677 |
|
|
MOVE_ENABLE : in bit;
|
678 |
|
|
COMP : in bit
|
679 |
|
|
);
|
680 |
|
|
end component;
|
681 |
|
|
|
682 |
|
|
component MLD_DPROP_5
|
683 |
|
|
port
|
684 |
|
|
(
|
685 |
|
|
DIN : in bit_vector(0 to 15);
|
686 |
|
|
DOUT : out bit_vector(14 downto 0);
|
687 |
|
|
FULL_OR : out bit
|
688 |
|
|
);
|
689 |
|
|
end component;
|
690 |
|
|
|
691 |
|
|
component ODA_REGISTER
|
692 |
|
|
port(
|
693 |
|
|
MOVE_IN : in bit_vector(15 downto 0);
|
694 |
|
|
MASK_IN : in bit;
|
695 |
|
|
CONTROL : in bit_vector(14 downto 0);
|
696 |
|
|
ENABLE : in bit;
|
697 |
|
|
CLK : in bit;
|
698 |
|
|
CLEAR : in bit;
|
699 |
|
|
RESET : in bit;
|
700 |
|
|
MASK_OUT : out bit;
|
701 |
|
|
MOVE_OUT : out bit_vector(15 downto 0)
|
702 |
|
|
);
|
703 |
|
|
end component;
|
704 |
|
|
|
705 |
|
|
|
706 |
|
|
-- Signal declarations
|
707 |
|
|
signal C_DOUT : bit_vector(63 downto 0);
|
708 |
|
|
signal C_MLOC : bit_vector(3 downto 0);
|
709 |
|
|
signal C_MLOC_INT_2: bit_vector(15 downto 0);
|
710 |
|
|
signal C_MLOC_INT_3: bit_vector(15 downto 0);
|
711 |
|
|
signal C_MTYPE : bit_vector(3 downto 0);
|
712 |
|
|
signal C_MTYPE_INT_2 : bit_vector (3 downto 0);
|
713 |
|
|
|
714 |
|
|
|
715 |
|
|
signal FULL_MATCH_VECTOR : bit_vector(15 downto 0);
|
716 |
|
|
signal MOVE : bit_vector(15 downto 1);
|
717 |
|
|
signal MOVE_ENABLE_INT : bit;
|
718 |
|
|
signal MOVE_ENABLE_INT_2 : bit;
|
719 |
|
|
signal MOVE_ENABLE_RLI : bit;
|
720 |
|
|
signal MTYPE_A : bit_vector(15 downto 0);
|
721 |
|
|
signal MTYPE_B : bit_vector(15 downto 0);
|
722 |
|
|
signal MTYPE_C : bit_vector(15 downto 0);
|
723 |
|
|
signal MTYPE_D : bit_vector(15 downto 0);
|
724 |
|
|
-- signal OVERFLOW : bit;
|
725 |
|
|
signal S_STRING : bit_vector(31 downto 0);
|
726 |
|
|
signal S_STRING_P0 : bit_vector(31 downto 0);
|
727 |
|
|
signal S_STRING_INT_2: bit_vector(31 downto 0);
|
728 |
|
|
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
signal U_DIN : bit_vector(31 downto 0);
|
732 |
|
|
|
733 |
|
|
signal FLUSH_INT_2: bit;
|
734 |
|
|
signal FLUSH_P0: bit;
|
735 |
|
|
signal COMP_INT_2: bit;
|
736 |
|
|
signal COMP_P0 : bit;
|
737 |
|
|
signal CAM_MASK :bit_vector(3 downto 0);
|
738 |
|
|
signal MASK_P0 : bit_vector(4 downto 0);
|
739 |
|
|
signal M_STRING : bit_vector(4 downto 0);
|
740 |
|
|
signal M_STRING_INT_2 : bit_vector(4 downto 0);
|
741 |
|
|
signal SAME_LENGTH_2 : bit_vector(15 downto 0);
|
742 |
|
|
signal SAME_LENGTH_2_P0 : bit_vector(15 downto 0);
|
743 |
|
|
signal SAME_LENGTH_3 : bit_vector(15 downto 0);
|
744 |
|
|
signal SAME_LENGTH_3_P0 : bit_vector(15 downto 0);
|
745 |
|
|
signal SAME_LENGTH_4 : bit_vector(15 downto 0);
|
746 |
|
|
signal SAME_LENGTH_4_P0 : bit_vector(15 downto 0);
|
747 |
|
|
signal SAME_POSITION : bit;
|
748 |
|
|
|
749 |
|
|
|
750 |
|
|
|
751 |
|
|
signal MTYPE_A_P0 : bit_vector(15 downto 0);
|
752 |
|
|
signal MTYPE_B_P0 : bit_vector(15 downto 0);
|
753 |
|
|
signal MTYPE_C_P0 : bit_vector(15 downto 0);
|
754 |
|
|
signal MTYPE_D_P0 : bit_vector(15 downto 0);
|
755 |
|
|
|
756 |
|
|
signal DOWN_PRIORITY_6 : bit_vector(15 downto 0);
|
757 |
|
|
signal DOWN_PRIORITY_5 : bit_vector(15 downto 0);
|
758 |
|
|
signal DOWN_PRIORITY_4 : bit_vector(15 downto 0);
|
759 |
|
|
signal DOWN_PRIORITY_3 : bit_vector(15 downto 0);
|
760 |
|
|
signal DOWN_PRIORITY_2 : bit_vector(15 downto 0);
|
761 |
|
|
signal DOWN_PRIORITY_1 : bit_vector(15 downto 0);
|
762 |
|
|
signal COLUMN_OR : bit_vector(6 downto 1);
|
763 |
|
|
|
764 |
|
|
signal DOWN_PRIORITY_6_P0 : bit_vector(15 downto 0);
|
765 |
|
|
signal DOWN_PRIORITY_5_P0 : bit_vector(15 downto 0);
|
766 |
|
|
signal DOWN_PRIORITY_4_P0 : bit_vector(15 downto 0);
|
767 |
|
|
signal DOWN_PRIORITY_3_P0 : bit_vector(15 downto 0);
|
768 |
|
|
signal DOWN_PRIORITY_2_P0 : bit_vector(15 downto 0);
|
769 |
|
|
signal DOWN_PRIORITY_1_P0 : bit_vector(15 downto 0);
|
770 |
|
|
signal COLUMN_OR_P0 : bit_vector(6 downto 1);
|
771 |
|
|
|
772 |
|
|
signal MOVE_AUX : bit_vector(15 downto 1); -- delete a loaded single byte a single byte
|
773 |
|
|
signal MOVE_INT : bit_vector(15 downto 0); -- Out of order adaptation
|
774 |
|
|
signal MOVE_DROP : bit_vector(15 downto 0);
|
775 |
|
|
|
776 |
|
|
signal INC_CAM,INC_INT,INC_INT_2,TABLE_FULL: bit;
|
777 |
|
|
|
778 |
|
|
signal NFL_M_ONE : bit_vector(7 downto 0);
|
779 |
|
|
|
780 |
|
|
signal M_STRING_ODA : bit; -- special case when waiting for buffer and single space search
|
781 |
|
|
|
782 |
|
|
--RLI signals
|
783 |
|
|
|
784 |
|
|
signal FULL_MATCH : bit;
|
785 |
|
|
signal FULL_MATCH_AT_ZERO : bit;
|
786 |
|
|
signal RL_DETECTED : bit;
|
787 |
|
|
signal RL_COUNT : bit_vector(7 downto 0);
|
788 |
|
|
signal RL_COUNT_DELAY : bit_vector(7 downto 0);
|
789 |
|
|
|
790 |
|
|
|
791 |
|
|
|
792 |
|
|
|
793 |
|
|
|
794 |
|
|
begin
|
795 |
|
|
-- Signal assignments
|
796 |
|
|
U_DIN <= U_DATAIN;
|
797 |
|
|
C_DATAOUT <= C_DOUT;
|
798 |
|
|
|
799 |
|
|
-- Component instances
|
800 |
|
|
SREG_1 : SREG
|
801 |
|
|
port map(
|
802 |
|
|
DIN => U_DIN,
|
803 |
|
|
MASK_IN => MASK,
|
804 |
|
|
CLEAR => CLEAR,
|
805 |
|
|
CLK => CLK,
|
806 |
|
|
MASK_OUT => MASK_P0,
|
807 |
|
|
QOUT => S_STRING_P0
|
808 |
|
|
);
|
809 |
|
|
|
810 |
|
|
MLD_LOGIC_1_1 : MLD_LOGIC_3_1_2
|
811 |
|
|
port map(
|
812 |
|
|
TYPE_A => MTYPE_A_P0,
|
813 |
|
|
TYPE_B => MTYPE_B_P0,
|
814 |
|
|
TYPE_C => MTYPE_C_P0,
|
815 |
|
|
TYPE_D => MTYPE_D_P0,
|
816 |
|
|
DOWN_PRIORITY_6 => DOWN_PRIORITY_6_P0,
|
817 |
|
|
DOWN_PRIORITY_5 => DOWN_PRIORITY_5_P0,
|
818 |
|
|
DOWN_PRIORITY_4 => DOWN_PRIORITY_4_P0,
|
819 |
|
|
DOWN_PRIORITY_3 => DOWN_PRIORITY_3_P0,
|
820 |
|
|
DOWN_PRIORITY_2 => DOWN_PRIORITY_2_P0,
|
821 |
|
|
DOWN_PRIORITY_1 => DOWN_PRIORITY_1_P0,
|
822 |
|
|
COLUMN_OR => COLUMN_OR_P0
|
823 |
|
|
);
|
824 |
|
|
|
825 |
|
|
PIPELINE_R0_0 : PIPELINE_R0
|
826 |
|
|
port map(
|
827 |
|
|
DOWN_PRIORITY_6_IN => DOWN_PRIORITY_6_P0,
|
828 |
|
|
DOWN_PRIORITY_5_IN => DOWN_PRIORITY_5_P0,
|
829 |
|
|
DOWN_PRIORITY_4_IN => DOWN_PRIORITY_4_P0,
|
830 |
|
|
DOWN_PRIORITY_3_IN => DOWN_PRIORITY_3_P0,
|
831 |
|
|
DOWN_PRIORITY_2_IN => DOWN_PRIORITY_2_P0,
|
832 |
|
|
DOWN_PRIORITY_1_IN => DOWN_PRIORITY_1_P0,
|
833 |
|
|
MATCH_TYPE_A_IN => MTYPE_A_P0,
|
834 |
|
|
MATCH_TYPE_B_IN => MTYPE_B_P0,
|
835 |
|
|
MATCH_TYPE_C_IN => MTYPE_C_P0,
|
836 |
|
|
MATCH_TYPE_D_IN => MTYPE_D_P0,
|
837 |
|
|
SAME_LENGTH_IN_2 => SAME_LENGTH_2_P0,
|
838 |
|
|
SAME_LENGTH_IN_3 => SAME_LENGTH_3_P0,
|
839 |
|
|
SAME_LENGTH_IN_4 => SAME_LENGTH_4_P0,
|
840 |
|
|
SEARCH_STRING_IN => S_STRING_P0,
|
841 |
|
|
MASK_IN => MASK_P0,
|
842 |
|
|
COLUMN_OR_IN => COLUMN_OR_P0,
|
843 |
|
|
FLUSH_IN => FLUSH,
|
844 |
|
|
COMP_IN => COMP,
|
845 |
|
|
MOVE_ENABLE_IN => MOVE_ENABLE,
|
846 |
|
|
INC_CAM_IN => MOVE(15), -- if move active then increment NFL
|
847 |
|
|
CLK => CLK,
|
848 |
|
|
CLEAR => CLEAR,
|
849 |
|
|
RESET => RESET,
|
850 |
|
|
DOWN_PRIORITY_6_OUT => DOWN_PRIORITY_6,
|
851 |
|
|
DOWN_PRIORITY_5_OUT => DOWN_PRIORITY_5,
|
852 |
|
|
DOWN_PRIORITY_4_OUT => DOWN_PRIORITY_4,
|
853 |
|
|
DOWN_PRIORITY_3_OUT => DOWN_PRIORITY_3,
|
854 |
|
|
DOWN_PRIORITY_2_OUT => DOWN_PRIORITY_2,
|
855 |
|
|
DOWN_PRIORITY_1_OUT => DOWN_PRIORITY_1,
|
856 |
|
|
MATCH_TYPE_A_OUT => MTYPE_A,
|
857 |
|
|
MATCH_TYPE_B_OUT => MTYPE_B,
|
858 |
|
|
MATCH_TYPE_C_OUT => MTYPE_C,
|
859 |
|
|
MATCH_TYPE_D_OUT => MTYPE_D,
|
860 |
|
|
SAME_LENGTH_OUT_2 => SAME_LENGTH_2,
|
861 |
|
|
SAME_LENGTH_OUT_3 => SAME_LENGTH_3,
|
862 |
|
|
SAME_LENGTH_OUT_4 => SAME_LENGTH_4,
|
863 |
|
|
SEARCH_STRING_OUT => S_STRING,
|
864 |
|
|
MASK_OUT => M_STRING,
|
865 |
|
|
COLUMN_OR_OUT => COLUMN_OR,
|
866 |
|
|
FLUSH_OUT => FLUSH_P0,
|
867 |
|
|
COMP_OUT => COMP_P0,
|
868 |
|
|
MOVE_ENABLE_OUT => MOVE_ENABLE_INT,
|
869 |
|
|
INC_CAM_OUT => INC_INT
|
870 |
|
|
);
|
871 |
|
|
|
872 |
|
|
-- C_FULL_HIT <= COLUMN_OR(5);
|
873 |
|
|
|
874 |
|
|
|
875 |
|
|
MLD_LOGIC_1_2 : MLD_LOGIC_3_2_2
|
876 |
|
|
port map(
|
877 |
|
|
MASK => M_STRING,
|
878 |
|
|
DOWN_PRIORITY_6 => DOWN_PRIORITY_6,
|
879 |
|
|
DOWN_PRIORITY_5 => DOWN_PRIORITY_5,
|
880 |
|
|
DOWN_PRIORITY_4 => DOWN_PRIORITY_4,
|
881 |
|
|
DOWN_PRIORITY_3 => DOWN_PRIORITY_3,
|
882 |
|
|
DOWN_PRIORITY_2 => DOWN_PRIORITY_2,
|
883 |
|
|
DOWN_PRIORITY_1 => DOWN_PRIORITY_1,
|
884 |
|
|
SAME_LENGTH_2 => SAME_LENGTH_2,
|
885 |
|
|
SAME_LENGTH_3 => SAME_LENGTH_3,
|
886 |
|
|
SAME_LENGTH_4 => SAME_LENGTH_4,
|
887 |
|
|
MATCH_TYPE_A => MTYPE_A,
|
888 |
|
|
MATCH_TYPE_B => MTYPE_B,
|
889 |
|
|
MATCH_TYPE_C => MTYPE_C,
|
890 |
|
|
MATCH_TYPE_D => MTYPE_D,
|
891 |
|
|
COLUMN_OR => COLUMN_OR,
|
892 |
|
|
MATCH_TYPE => C_MTYPE_INT_2,
|
893 |
|
|
MATCH_LOC => C_MLOC_INT_2
|
894 |
|
|
);
|
895 |
|
|
|
896 |
|
|
|
897 |
|
|
MC_MUX_1 : MC_MUX_3C
|
898 |
|
|
port map(
|
899 |
|
|
A => MOVE_DROP,
|
900 |
|
|
ENABLEC => MOVE_ENABLE,
|
901 |
|
|
Y => MOVE_INT
|
902 |
|
|
);
|
903 |
|
|
|
904 |
|
|
|
905 |
|
|
ODA_REGISTER_1 : ODA_REGISTER
|
906 |
|
|
port map(
|
907 |
|
|
MASK_IN => MASK_P0(3),
|
908 |
|
|
MOVE_IN => FULL_MATCH_VECTOR,
|
909 |
|
|
CONTROL => MOVE,
|
910 |
|
|
ENABLE => MOVE_ENABLE,
|
911 |
|
|
CLK => CLK,
|
912 |
|
|
CLEAR => CLEAR,
|
913 |
|
|
RESET => RESET,
|
914 |
|
|
MASK_OUT => M_STRING_ODA,
|
915 |
|
|
MOVE_OUT => MOVE_DROP
|
916 |
|
|
);
|
917 |
|
|
|
918 |
|
|
|
919 |
|
|
NFL_COUNTERS_1: NFL_COUNTERS2
|
920 |
|
|
port map(
|
921 |
|
|
INC => INC_INT_2, --INC_INT_2
|
922 |
|
|
COUNT_ENABLE => MOVE_ENABLE_INT_2, -- MOVE_ENABLE_INT_2,
|
923 |
|
|
CLK => CLK,
|
924 |
|
|
RESET => RESET,
|
925 |
|
|
CLEAR => CLEAR,
|
926 |
|
|
NFL_MINUS_ONE => NFL_M_ONE,
|
927 |
|
|
TABLE_FULL => TABLE_FULL
|
928 |
|
|
);
|
929 |
|
|
|
930 |
|
|
|
931 |
|
|
|
932 |
|
|
MOVE_GENERATION : MLD_DPROP_5 port map ( DIN => MOVE_INT,
|
933 |
|
|
DOUT => MOVE_AUX,
|
934 |
|
|
FULL_OR => open
|
935 |
|
|
);
|
936 |
|
|
|
937 |
|
|
|
938 |
|
|
FULL_MATCH_D_1 : FULL_MATCH_D
|
939 |
|
|
port map(
|
940 |
|
|
NFL_M_ONE => NFL_M_ONE,
|
941 |
|
|
MOVE_ENABLE => MOVE_ENABLE,
|
942 |
|
|
PRIORITY_6 => DOWN_PRIORITY_6_P0,
|
943 |
|
|
PRIORITY_5 => DOWN_PRIORITY_5_P0,
|
944 |
|
|
PRIORITY_2 => DOWN_PRIORITY_2_P0,
|
945 |
|
|
SAME_LENGTH_2 => SAME_LENGTH_2_P0,
|
946 |
|
|
SAME_LENGTH_3 => SAME_LENGTH_3_P0,
|
947 |
|
|
SAME_LENGTH_4 => SAME_LENGTH_4_P0,
|
948 |
|
|
CLK => CLK,
|
949 |
|
|
CLEAR => CLEAR,
|
950 |
|
|
RESET => RESET,
|
951 |
|
|
FULL_MATCH => FULL_MATCH, -- full match at any position
|
952 |
|
|
FULL_MATCH_AT_ZERO => FULL_MATCH_AT_ZERO, -- full match at zero location
|
953 |
|
|
SAME_POSITION => SAME_POSITION,
|
954 |
|
|
FULL_MATCH_VECTOR => FULL_MATCH_VECTOR
|
955 |
|
|
);
|
956 |
|
|
|
957 |
|
|
|
958 |
|
|
|
959 |
|
|
MOVE <= MOVE_AUX when M_STRING_ODA = '1' else "000000000000000"; --if single space manipulate move vector
|
960 |
|
|
|
961 |
|
|
|
962 |
|
|
CAM_MASK <= MASK_P0(4 downto 1);
|
963 |
|
|
|
964 |
|
|
CAM_ARRAY_1 : CAM_ARRAY_ZERO
|
965 |
|
|
port map(
|
966 |
|
|
SEARCH_DATA => S_STRING_P0,
|
967 |
|
|
SEARCH_MASK => CAM_MASK,
|
968 |
|
|
PREVIOUS_DATA => S_STRING_P0,
|
969 |
|
|
PREVIOUS_MASK => CAM_MASK,
|
970 |
|
|
ENABLE => MOVE_ENABLE, -- do not load tuple 0 when waiting for data from the buffer
|
971 |
|
|
MOVE => MOVE,
|
972 |
|
|
CLEAR => CLEAR,
|
973 |
|
|
RESET => RESET,
|
974 |
|
|
CLK => CLK,
|
975 |
|
|
SAME_LENGTH_2 => SAME_LENGTH_2_P0,
|
976 |
|
|
SAME_LENGTH_3 => SAME_LENGTH_3_P0,
|
977 |
|
|
SAME_LENGTH_4 => SAME_LENGTH_4_P0,
|
978 |
|
|
MTYPE_A => MTYPE_A_P0,
|
979 |
|
|
MTYPE_B => MTYPE_B_P0,
|
980 |
|
|
MTYPE_C => MTYPE_C_P0,
|
981 |
|
|
MTYPE_D => MTYPE_D_P0
|
982 |
|
|
);
|
983 |
|
|
|
984 |
|
|
|
985 |
|
|
PIPELINE_R1_1 : PIPELINE_R1
|
986 |
|
|
port map(
|
987 |
|
|
MATCH_LOC_IN => C_MLOC_INT_2,
|
988 |
|
|
MATCH_TYPE_IN => C_MTYPE_INT_2,
|
989 |
|
|
SEARCH_STRING_IN=>S_STRING,
|
990 |
|
|
MASK_IN=> M_STRING,
|
991 |
|
|
FLUSH_IN=>FLUSH_P0,
|
992 |
|
|
COMP_IN=>COMP_P0,
|
993 |
|
|
MOVE_ENABLE_IN => MOVE_ENABLE_INT,
|
994 |
|
|
INC_IN => INC_INT,
|
995 |
|
|
CLEAR=>CLEAR,
|
996 |
|
|
RESET=>RESET,
|
997 |
|
|
CLK=>CLK,
|
998 |
|
|
MATCH_LOC_OUT => C_MLOC_INT_3,
|
999 |
|
|
MATCH_TYPE_OUT => C_MTYPE,
|
1000 |
|
|
SEARCH_STRING_OUT=>S_STRING_INT_2,
|
1001 |
|
|
MASK_OUT => M_STRING_INT_2,
|
1002 |
|
|
FLUSH_OUT=>FLUSH_INT_2,
|
1003 |
|
|
COMP_OUT=>COMP_INT_2,
|
1004 |
|
|
MOVE_ENABLE_OUT => MOVE_ENABLE_INT_2,
|
1005 |
|
|
INC_OUT => INC_INT_2
|
1006 |
|
|
);
|
1007 |
|
|
|
1008 |
|
|
ENCODE16_5 : ENCODE16_4
|
1009 |
|
|
port map(
|
1010 |
|
|
MATCH_LOC_IN => C_MLOC_INT_3,
|
1011 |
|
|
MATCH_LOC_OUT => C_MLOC
|
1012 |
|
|
);
|
1013 |
|
|
|
1014 |
|
|
|
1015 |
|
|
DELAY : COUNT_DELAY
|
1016 |
|
|
port map(
|
1017 |
|
|
COUNT_IN => RL_COUNT,
|
1018 |
|
|
CLEAR => CLEAR,
|
1019 |
|
|
RESET => RESET,
|
1020 |
|
|
CLK => CLK,
|
1021 |
|
|
COUNT_OUT => RL_COUNT_DELAY
|
1022 |
|
|
);
|
1023 |
|
|
|
1024 |
|
|
MOVE_ENABLE_RLI <= MOVE_ENABLE;
|
1025 |
|
|
|
1026 |
|
|
RLI_C : RLI_COUNTER_C
|
1027 |
|
|
port map(
|
1028 |
|
|
MOVE_ENABLE => MOVE_ENABLE_RLI,
|
1029 |
|
|
ENABLE_C => FULL_MATCH, -- full match at any position
|
1030 |
|
|
LOCATION_ZERO => FULL_MATCH_AT_ZERO, -- full match at location zero
|
1031 |
|
|
SAME_POSITION => SAME_POSITION, -- second match at the same position
|
1032 |
|
|
CLEAR => CLEAR,
|
1033 |
|
|
RESET => RESET,
|
1034 |
|
|
CLK => CLK,
|
1035 |
|
|
COUNT => RL_COUNT,
|
1036 |
|
|
RL_DETECTED => RL_DETECTED
|
1037 |
|
|
);
|
1038 |
|
|
|
1039 |
|
|
CG_ASSEMBLY_1 : CG_ASSEMBLY
|
1040 |
|
|
port map(
|
1041 |
|
|
RL_DETECTED => RL_DETECTED,
|
1042 |
|
|
COUNT_IN => RL_COUNT_DELAY,
|
1043 |
|
|
TABLE_FULL => TABLE_FULL,
|
1044 |
|
|
NFL_M_ONE => NFL_M_ONE(3 downto 0),
|
1045 |
|
|
SEARCH_STRING => S_STRING_INT_2,
|
1046 |
|
|
MASK => M_STRING_INT_2,
|
1047 |
|
|
MATCH_TYPE => C_MTYPE,
|
1048 |
|
|
MATCH_LOC => C_MLOC,
|
1049 |
|
|
CLEAR => CLEAR,
|
1050 |
|
|
RESET => RESET,
|
1051 |
|
|
CLK => CLK,
|
1052 |
|
|
FLUSH => FLUSH_INT_2,
|
1053 |
|
|
FLUSH_RLI => FLUSH_P0,
|
1054 |
|
|
OVERFLOW => OVERFLOW,
|
1055 |
|
|
SHORT => SHORT,
|
1056 |
|
|
DOUT => C_DOUT,
|
1057 |
|
|
FLUSH_END => FLUSH_END,
|
1058 |
|
|
MOVE_ENABLE => MOVE_ENABLE_INT_2,
|
1059 |
|
|
COMP => COMP_INT_2
|
1060 |
|
|
);
|
1061 |
|
|
|
1062 |
|
|
|
1063 |
|
|
end level2_4ca;
|