Subversion Repositories xmatchpro

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity xmatch_controller is

port

(

        rst_CODMU       : IN STD_LOGIC;

        clk_CODMU       : IN STD_LOGIC;

        rst_HOST                : IN STD_LOGIC;

        clk_HOST        : IN STD_LOGIC;

        din_HOST        : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

        wr_en_HOST      : IN STD_LOGIC;

        rd_en_HOST      : IN STD_LOGIC;

        dout_HOST       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

        full_HOST       : OUT STD_LOGIC;

        empty_HOST      : OUT STD_LOGIC;

        command_CR_HOST : in std_logic_vector(31 DOWNTO 0);

        status_CDI_HOST : out std_logic_vector(31 DOWNTO 0)

);

end xmatch_controller;

architecture Behavioral of xmatch_controller is

component level1r is port

(

        CS                                                              : in bit ;

        RW                                                              : in bit;

        ADDRESS                                                 : in bit_vector(3 downto 0);

        CONTROL_IN                                              : in std_logic_vector(31 downto 0);

        CONTROL_OUT_C                                   : out std_logic_vector (31 downto 0);

        CONTROL_OUT_D                                   : out std_logic_vector (31 downto 0);

        CLK                                                             : in bit ;

        CLEAR                                                           : in bit;

        BUS_ACKNOWLEDGE_CC                      : in bit;

        BUS_ACKNOWLEDGE_CU                      : in bit;

        BUS_ACKNOWLEDGE_DC                      : in bit;

        BUS_ACKNOWLEDGE_DU                      : in bit;

        WAIT_CU                                                 : in bit;

        WAIT_CC                                                         : in bit;

        WAIT_DC                                                         : in bit;

        WAIT_DU                                                         : in bit;

        U_DATAIN                                                : in bit_vector(31 downto 0);

        C_DATAIN                                                : in bit_vector(31 downto 0);

        U_DATAOUT                                               : out std_logic_vector(31 downto 0);

        C_DATAOUT                                               : out std_logic_vector(31 downto 0);

        FINISHED_C                                              : out bit;

        FINISHED_D                                              : out bit;

        COMPRESSING                                     : out bit;

        FLUSHING_C                                              : out bit;

        FLUSHING_D                                              : out bit;

        DECOMPRESSING                                   : out bit;

        U_DATA_VALID                                    : out bit;

        C_DATA_VALID                                    : out bit;

        DECODING_OVERFLOW                       : out bit;

        CODING_OVERFLOW                                 : out bit;

        CRC_ERROR                                               : out bit;

        INTERRUPT_REQUEST                       : out bit;

        INTERRUPT_ACKNOWLEDGE           : in bit;

        BUS_REQUEST_CC                          : out bit;

        BUS_REQUEST_CU                          : out bit;

        BUS_REQUEST_DC                          : out bit;

        BUS_REQUEST_DU                          : out bit

);

end component;

--

--  component fifo_32x512

--    port (

--      clk: IN std_logic;

--      srst: IN std_logic;

--      din: IN std_logic_VECTOR(31 downto 0);

--      wr_en: IN std_logic;

--      rd_en: IN std_logic;

--      dout: OUT std_logic_VECTOR(31 downto 0);

--      full: OUT std_logic;

--      empty: OUT std_logic);

--  end component;

component fifo_32x512 is port

(

    rst : IN STD_LOGIC;

    wr_clk : IN STD_LOGIC;

    rd_clk : IN STD_LOGIC;

    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    wr_en : IN STD_LOGIC;

    rd_en : IN STD_LOGIC;

    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

    full : OUT STD_LOGIC;

    empty : OUT STD_LOGIC

  );

end component;

-- All signals to convert from std_logic to bit

signal CS_bit                                           : bit;

signal RW_bit                                           : bit;

signal ADDRESS_bit                              : bit_vector (3 downto 0);

signal CONTROL_std                              : std_logic_vector (31 downto 0);

signal CLK_bit                                  : bit;

signal CLEAR_bit                                        : bit;

signal BUS_ACKNOWLEDGE_CC_bit   : bit := '1';

signal BUS_ACKNOWLEDGE_CU_bit   : bit := '1';

signal BUS_ACKNOWLEDGE_DC_bit   : bit := '1';

signal BUS_ACKNOWLEDGE_DU_bit : bit := '1';

signal WAIT_CU_bit                              : bit;

signal WAIT_CC_bit                              : bit;

signal WAIT_DC_bit                              : bit;

signal WAIT_DU_bit                              : bit;

signal U_DATAIN_bit                             : bit_vector (31 downto 0);

signal C_DATAIN_bit                             : bit_vector (31 downto 0);

signal C_DATAOUT_std                            : std_logic_vector (31 downto 0);

signal U_DATAOUT_std                            : std_logic_vector (31 downto 0);

signal FINISHED_C_bit                   : bit;

signal FINISHED_D_bit                   : bit;

signal U_DATA_VALID_bit                 : bit;

signal C_DATA_VALID_bit                 : bit;

signal INTERUPT_ACKNWLDGE_bit : bit;

signal BUS_REQUEST_CC_bit               : bit;

signal BUS_REQUEST_CU_bit               : bit;

signal BUS_REQUEST_DC_bit               : bit;

signal BUS_REQUEST_DU_bit               : bit;

signal COMPRESSING_bit                  : bit;

signal FLUSHING_C_bit                   : bit;

signal FLUSHING_D_bit                   : bit;

signal DECOMPRESSING_bit                : bit;

signal DECODING_OVERFLOW_bit    : bit;

signal CODING_OVERFLOW_bit      : bit;

signal CRC_ERROR_bit                            : bit;

signal INTERRUPT_REQUEST_bit    : bit;

signal U_DATAIN_reg                             : std_logic_vector(31 downto 0);

signal C_DATAIN_reg                             : std_logic_vector(31 downto 0);

-- Signals used for FIFO

signal FIFO_read_signal                 : std_logic := '0';

signal FIFO_data_out                            : std_logic_vector(31 downto 0);

signal FIFO_write_signal                : std_logic := '0';

signal FIFO_data_in                             : std_logic_vector(31 downto 0);

-- State machine

type states is  (       IDLE,

                                                COMPRESS_START,

                                                COMPRESS_START1,

                                                COMPRESS_START2,

                                                COMPRESS_INIT_BLOCKSIZE,

                                                COMPRESS_INIT_COMMAND,

                                                COMPRESS_WAIT_FILESIZE,

                                                COMPRESS_WAIT,

                                                COMPRESS_WAIT_BUS_ACK_CU,

                                                COMPRESS_WAIT_SEND,

                                                COMPRESS_SEND_DATA,

                                                COMPRESS_WAIT_REQ_CU,

                                                COMPRESS_WAIT_CU_SEND,

                                                COMPRESS_WAIT_INTERRUPT_REQUEST,

                                                COMPRESS_WAIT_NEXT_PACKET,

                                                DECOMPRESS_START,

                                                DECOMPRESS_START1,

                                                DECOMPRESS_START2,

                                                DECOMPRESS_INIT_BLOCKSIZE,

                                                DECOMPRESS_INIT_COMMAND,

                                                DECOMPRESS_WAIT,

                                                DECOMPRESS_WAIT_BUS_ACK_DC,

                                                DECOMPRESS_WAIT_SEND,

                                                DECOMPRESS_SEND_DATA,

                                                DECOMPRESS_WAIT_REQ_DC,

                                                DECOMPRESS_WAIT_DC_SEND,

                                                DECOMPRESS_WAIT_FINISH_DC,

                                                DECOMPRESS_WAIT_INTERRUPT_REQUEST,

                                                DECOMPRESS_WAIT_NEXT_PACKET,

                                                END_STATE);

signal cur_state     : states;

signal next_state    : states;

signal reg_ADDRESS              :  std_logic_vector(3 downto 0);

signal reg_CONTROL              :  std_logic_vector(3 downto 0);

signal reg_THRESHOLD            :  std_logic_vector(7 downto 0);

signal reg_BLOCKSIZE            :  std_logic_vector(15 downto 0);

signal full_CODMU               :  STD_LOGIC;

signal empty_CODMU              :  STD_LOGIC;

signal clr_CODMU                        :  STD_LOGIC;

signal CLR_XMATCH_C             :  STD_LOGIC := '1';

signal CLR_XMATCH_D             :  STD_LOGIC := '1';

signal reg_STATUS_CDI   :  std_logic_vector(31 downto 0) := x"00000001";

signal reg_FILESIZE : std_logic_vector(28 downto 0) := (others => '0');

signal counter_BLOCKSIZE : std_logic_vector(15 downto 0) := x"0000"; -- used for check if the uncompressed file almost reach 0

begin

status_CDI_HOST <= reg_STATUS_CDI;

xmatchpro : level1r

port map (

        CS                                                      => CS_bit,

        RW                                                      => RW_bit,

        ADDRESS                                                 => ADDRESS_bit,

        CONTROL_IN                                      => CONTROL_std,

        CONTROL_OUT_C                           => open,

        CONTROL_OUT_D                           => open,

        CLK                                                     => CLK_bit,

        CLEAR                                           => CLEAR_bit,

        BUS_ACKNOWLEDGE_CC              => BUS_ACKNOWLEDGE_CC_bit,

        BUS_ACKNOWLEDGE_CU              => BUS_ACKNOWLEDGE_CU_bit,

        BUS_ACKNOWLEDGE_DC              => BUS_ACKNOWLEDGE_DC_bit,

        BUS_ACKNOWLEDGE_DU              => BUS_ACKNOWLEDGE_DU_bit,

        WAIT_CU                                                 => WAIT_CU_bit,

   WAIT_CC                                              => WAIT_CC_bit,

   WAIT_DC                                              => WAIT_DC_bit,

        WAIT_DU                                                 => WAIT_DU_bit,

        U_DATAIN                                        => U_DATAIN_bit,

        C_DATAIN                                        => C_DATAIN_bit,

        U_DATAOUT                                       => U_DATAOUT_std,

        C_DATAOUT                                       => C_DATAOUT_std,

        FINISHED_C                                      => FINISHED_C_bit,

        FINISHED_D                                      => FINISHED_D_bit,

        COMPRESSING                             => COMPRESSING_bit,

        FLUSHING_C                                      => FLUSHING_C_bit,

        FLUSHING_D                                      => FLUSHING_D_bit,

        DECOMPRESSING                           => DECOMPRESSING_bit,

        U_DATA_VALID                            => U_DATA_VALID_bit,

        C_DATA_VALID                            => C_DATA_VALID_bit,

        DECODING_OVERFLOW               => DECODING_OVERFLOW_bit,

        CODING_OVERFLOW                         => CODING_OVERFLOW_bit,

        CRC_ERROR                                       => CRC_ERROR_bit,

        INTERRUPT_REQUEST               => INTERRUPT_REQUEST_bit,

        INTERRUPT_ACKNOWLEDGE   => INTERUPT_ACKNWLDGE_bit,

        BUS_REQUEST_CC                  => BUS_REQUEST_CC_bit,

        BUS_REQUEST_CU                  => BUS_REQUEST_CU_bit,

        BUS_REQUEST_DC                  => BUS_REQUEST_DC_bit,

        BUS_REQUEST_DU                  => BUS_REQUEST_DU_bit

);

---- FIFO Loopback

--FIFO_loopback : fifo_32x512

--  PORT MAP (

--    rst => not rst_HOST,

--       wr_clk => clk_HOST,

--       rd_clk => clk_HOST,

--    din => din_HOST,

--    wr_en => wr_en_HOST,

--    rd_en => rd_en_HOST,

--    dout => dout_HOST,

--    full => full_HOST,

--    empty => empty_HOST

--  );

FIFO_HOST2CODMU : fifo_32x512

  PORT MAP (

    rst => not rst_HOST,

         wr_clk => clk_HOST,

         rd_clk => clk_CODMU,

    din => din_HOST,

    wr_en => wr_en_HOST,

    rd_en => FIFO_read_signal,

    dout => FIFO_data_out,

    full => full_HOST,

    empty => empty_CODMU

  );

-- rst_CODMU was replaced with rst_HOST in FIFO_CODMU2HOST

FIFO_CODMU2HOST : fifo_32x512

  PORT MAP (

    rst => not rst_HOST,

         wr_clk => clk_CODMU,

         rd_clk => clk_HOST,

    din => FIFO_data_in,

    wr_en => FIFO_write_signal,

    rd_en => rd_en_HOST,

    dout => dout_HOST,

    full => full_CODMU,

    empty => empty_HOST

  );

-- Clock and Reset Declaration, convert from std_logic to bit to be used in Xmatch

CLK_bit         <= to_bit (clk_CODMU);

--CLEAR_bit     <= (to_bit (rst_CODMU)) and ((to_bit (CLR_XMATCH_C)) xor (to_bit (not CLR_XMATCH_D)));

CLEAR_bit       <= (to_bit (rst_HOST)) and ((to_bit (CLR_XMATCH_C)) xor (to_bit (not CLR_XMATCH_D)));

-- Note: This is bit mapping of Bus2IP_Data example

-- Bus2IP_Data <= "1101 1100 00001000 0000000000100000";

-- 1101 is the Compression Channel at R1C Register called Uncompressed Block Size Register for ADDRESS

-- 1100 is the Compression Channel at R0C Register called Command Register for CONTROL

-- 00001000 is equivalent to 8 for THRESHOLD

-- 0000000000100000 is equivalent to 32 which means 32 Bytes size

-- The IP Core read from source address and send in both U_DATAIN and C_DATAIN

-- The state machine will decide which will be used for Compression/Decompression

U_DATAIN_bit <= to_bitvector (U_DATAIN_reg);

C_DATAIN_bit <= to_bitvector (C_DATAIN_reg);

U_DATAIN_PROCESS : process (clk_CODMU, clr_CODMU, FIFO_read_signal)

begin

if (clr_CODMU = '0') then

        U_DATAIN_reg <= x"00000000";

elsif ((clk_CODMU'event) and (clk_CODMU = '1')) then

        if (rst_HOST = '0') then

                U_DATAIN_reg <= x"00000000";

        elsif (FIFO_read_signal = '1') then

                U_DATAIN_reg <= FIFO_data_out;

        else

                U_DATAIN_reg <= U_DATAIN_reg;

        end if;

end if;

end process U_DATAIN_PROCESS;

C_DATAIN_PROCESS : process (clk_CODMU, clr_CODMU, FIFO_read_signal)

begin

if (clr_CODMU = '0') then

        C_DATAIN_reg <= x"00000000";

elsif ((clk_CODMU'event) and (clk_CODMU = '1')) then

        if (rst_HOST = '0') then

                C_DATAIN_reg <= x"00000000";

        elsif (FIFO_read_signal = '1') then

                C_DATAIN_reg <= FIFO_data_out;

        else

                C_DATAIN_reg <= C_DATAIN_reg;

        end if;

end if;

end process C_DATAIN_PROCESS;

-- Acknowledgement bus from Compressor and Decompressor

-- CU is from Compressor to compress from Uncompressed

BUS_ACKNOWLEDGE_CU_PROCESS: process (clk_CODMU, clr_CODMU) is

begin

if (clr_CODMU = '0') then

        BUS_ACKNOWLEDGE_CU_bit <= '1';

elsif ((clk_CODMU'event) and (clk_CODMU = '1')) then

        if (BUS_REQUEST_CU_bit = '1') then

      BUS_ACKNOWLEDGE_CU_bit            <= '1';

        else

      BUS_ACKNOWLEDGE_CU_bit            <= '0';

  end if;

 end if;

end process BUS_ACKNOWLEDGE_CU_PROCESS;

BUS_ACKNOWLEDGE_DC_PROCESS: process (clk_CODMU, clr_CODMU) is

begin

if (clr_CODMU = '0') then

        BUS_ACKNOWLEDGE_DC_bit <= '1';

elsif ((clk_CODMU'event) and (clk_CODMU = '1')) then

        if (BUS_REQUEST_DC_bit = '1') then

      BUS_ACKNOWLEDGE_DC_bit            <= '1';

        else

      BUS_ACKNOWLEDGE_DC_bit            <= '0';

  end if;

 end if;

end process BUS_ACKNOWLEDGE_DC_PROCESS;

-- CC is from Compressor to compress becomes Compressed

-- DC is from Decompressor to decompress from Compressed

-- DU is from Decompressor to decompress becomes Uncompressed

--BUS_ACKNOWLEDGE_CU_bit <= BUS_REQUEST_CU_bit;

BUS_ACKNOWLEDGE_CC_bit <= BUS_REQUEST_CC_bit;

BUS_ACKNOWLEDGE_DU_bit <= BUS_REQUEST_DU_bit;

COMMAND_CR_PROCESS: process (clk_CODMU, clr_CODMU, command_CR_HOST) is

begin

if (clr_CODMU = '0') then

        reg_ADDRESS     <= (others => '0');

        reg_CONTROL     <= (others => '0');

        reg_THRESHOLD   <= (others => '0');

        reg_BLOCKSIZE   <= (others => '0');

        reg_FILESIZE    <= (others => '0');

elsif ((clk_CODMU'event) and (clk_CODMU = '1')) then

        case (command_CR_HOST(29 downto 28)) is

                when "01" => -- If the controller receive compress/decompress request, then save these 4 CR informations into registers

                        reg_ADDRESS     <= command_CR_HOST(31 downto 28);

                        reg_CONTROL     <= command_CR_HOST(27 downto 24);

                        reg_THRESHOLD   <= command_CR_HOST(23 downto 16);

                        reg_BLOCKSIZE   <= command_CR_HOST(15 downto  0);

                        reg_FILESIZE    <= (others => '0');

                when "10" => -- in C language, use bitwise OR operation | with 0x20000000 for filesize with optimized-compression, max filesize: 512 MB

                        reg_FILESIZE    <= command_CR_HOST(28 downto 0);

                when "11" => -- in C language, use bitwise OR operation | with 0x30000000 for filesize without optimized-compression, maxfilesize: 2^28 = 256 MB

                        reg_FILESIZE    <= '0' & command_CR_HOST(27 downto 0);

                when others =>

                        reg_ADDRESS     <= reg_ADDRESS;

                        reg_CONTROL     <= reg_CONTROL;

                        reg_THRESHOLD   <= reg_THRESHOLD;

                        reg_BLOCKSIZE   <= reg_BLOCKSIZE;

                        reg_FILESIZE    <= reg_FILESIZE;

        end case;

 end if;

end process COMMAND_CR_PROCESS;

COUNTER_BLOCKSIZE_PROCESS: process (clk_CODMU, clr_CODMU, cur_state, FIFO_read_signal, U_DATAIN_reg) is

begin

        if ((clk_CODMU'event) and (clk_CODMU = '1')) then

                if FIFO_read_signal = '1' and U_DATAIN_reg /= x"00000000" then

                        counter_BLOCKSIZE <= counter_BLOCKSIZE - 4;

                elsif (cur_state = COMPRESS_INIT_BLOCKSIZE) then -- if either Compress or Decompress

                        counter_BLOCKSIZE <= reg_BLOCKSIZE; -- blocksize

                else

                        counter_BLOCKSIZE <= counter_BLOCKSIZE;

                end if;

        end if;

end process COUNTER_BLOCKSIZE_PROCESS;

-- State machine sequence (synchronous process)

SM_SEQ: process (clk_CODMU, rst_HOST) is

begin

  if clk_CODMU'event and clk_CODMU = '1' then

    if rst_HOST = '0' then

      cur_state                         <= IDLE;

    else

      cur_state                         <= next_state;

    end if;

  end if;

end process SM_SEQ;

-- State machine (combinatorial process)

SM_COMB: process (cur_state, reg_ADDRESS, reg_FILESIZE, counter_BLOCKSIZE,

                                                BUS_REQUEST_CU_bit, FINISHED_C_bit, U_DATAIN_reg,

                                                BUS_REQUEST_DC_bit, FINISHED_D_bit, C_DATAIN_reg,

                                                wr_en_HOST, empty_CODMU, INTERRUPT_REQUEST_bit,

                                                COMPRESSING_bit, DECOMPRESSING_bit) is

begin

next_state                                              <= cur_state;           -- default remain current state          

CS_bit                                                  <= '1';

RW_bit                                                  <= '1';

ADDRESS_bit                                             <= "0011";                      -- "0011" is an unused Address which not be used by Compressor/Decompressor

CONTROL_std                                             <= x"00000000";

WAIT_CU_bit                                     <= '0';

WAIT_CC_bit                                     <= '1';

WAIT_DC_bit                                     <= '0';

WAIT_DU_bit                                     <= '1';

INTERUPT_ACKNWLDGE_bit          <= '1';

FIFO_read_signal                                <= '0';

clr_CODMU                                               <= '1';

CLR_XMATCH_C                                    <= '1';

CLR_XMATCH_D                                    <= '1';

reg_STATUS_CDI                          <= x"00000001";

case cur_state is

        when IDLE =>

                reg_STATUS_CDI <= x"00000002";

                case (reg_ADDRESS) is

                        when "1101" => next_state <=   COMPRESS_START;

                        when "1001" => next_state <= DECOMPRESS_START;

                        when others => next_state <= IDLE;

                end case;

        when COMPRESS_START =>

                CLR_XMATCH_C <= '0';

                next_state <=   COMPRESS_START1;

        when COMPRESS_START1 =>

                next_state <=   COMPRESS_START2;

        when COMPRESS_START2 =>

                next_state <=   COMPRESS_INIT_BLOCKSIZE;

        when COMPRESS_INIT_BLOCKSIZE =>

                reg_STATUS_CDI <= x"00000003";

                RW_bit                                                  <= '0';

                CS_bit                                                  <= '0';

                ADDRESS_bit                                             <= to_bitvector (reg_ADDRESS);

                CONTROL_std                                             <= x"0000" & reg_BLOCKSIZE;

                next_state                                              <= COMPRESS_INIT_COMMAND;

        when COMPRESS_INIT_COMMAND =>

                reg_STATUS_CDI <= x"00000004";

                RW_bit                                                  <= '0';

                CS_bit                                                  <= '0';

                ADDRESS_bit                                             <= to_bitvector (reg_CONTROL);

                CONTROL_std                                             <= "0000000000000000" & "0100" & reg_THRESHOLD & "0000";

                next_state                                              <= COMPRESS_WAIT_FILESIZE;

        when COMPRESS_WAIT_FILESIZE =>

                reg_STATUS_CDI <= x"00000009";

                if reg_FILESIZE /= x"00000000" then -- if controller has not received the filesize information yet

                        next_state                      <= COMPRESS_WAIT;

                else

                        next_state                      <= COMPRESS_WAIT_FILESIZE;

                end if;

        -- Compression wait if bus request CU is ready, and the FIFO of CoDMU is not empty (has data)

        when COMPRESS_WAIT =>

                reg_STATUS_CDI <= x"00000005";

                if BUS_REQUEST_CU_bit = '0' and empty_CODMU = '0' then

                        next_state                      <= COMPRESS_WAIT_BUS_ACK_CU;

                else

                        next_state                      <= COMPRESS_WAIT;

                end if;

        -- Wait for 1 clock cycle of Bus Ack CU

        when COMPRESS_WAIT_BUS_ACK_CU =>

                next_state                      <= COMPRESS_WAIT_SEND;

        -- FIFO read signal has one delay clock cycle, before Wait CU is asserted

        when COMPRESS_WAIT_SEND =>

                if U_DATAIN_reg /= x"00000000" then

                        WAIT_CU_bit <= '1'; -- the WAIT_CU will not be triggered if the first word is 0, due to absence of First Word Fall Through FIFO

                end if;

                FIFO_read_signal <= '1';

                next_state <= COMPRESS_SEND_DATA;

        -- Send data from FIFO to Xmatch

        when COMPRESS_SEND_DATA =>

                --WAIT_CU_bit <= '1';

                if U_DATAIN_reg /= x"00000000" then

                        WAIT_CU_bit <= '1'; -- the WAIT_CU will not be triggered if the first word is 0, due to absence of First Word Fall Through FIFO

                end if;

                if counter_BLOCKSIZE = x"0000" then

                        next_state <= COMPRESS_WAIT_REQ_CU;

                elsif BUS_REQUEST_CU_bit = '1' then

                        next_state <= COMPRESS_WAIT_REQ_CU;

                else

                        FIFO_read_signal <= '1';

                        next_state <= COMPRESS_SEND_DATA;

                end if;

        -- Wait if Bus Request CU is availabe (0) again

        when COMPRESS_WAIT_REQ_CU =>

                WAIT_CU_bit <= '1';

                if BUS_REQUEST_CU_bit = '0' then

                        next_state                      <= COMPRESS_WAIT_CU_SEND;

                elsif FINISHED_C_bit = '0' then

                        next_state                      <= COMPRESS_WAIT_INTERRUPT_REQUEST;

                else

                        next_state                      <= COMPRESS_WAIT_REQ_CU;

                end if;

        -- Read the first data goes out before read from FIFO again

        when COMPRESS_WAIT_CU_SEND =>

                WAIT_CU_bit <= '1';

                next_state      <= COMPRESS_SEND_DATA;

        when COMPRESS_WAIT_INTERRUPT_REQUEST =>

                if INTERRUPT_REQUEST_bit = '0' then

                        INTERUPT_ACKNWLDGE_bit <= '0';

                        clr_CODMU               <= '0';

                        next_state              <= IDLE;

                else

                        next_state              <= COMPRESS_WAIT_NEXT_PACKET;

                end if;

        when COMPRESS_WAIT_NEXT_PACKET =>

                if empty_CODMU = '0' then -- check if any packet left

                        CLR_XMATCH_C <= '0';

                        next_state <= COMPRESS_START; -- it will automatically starts Compressor Mode because there is still data available

                else

                        clr_CODMU       <= '0';

                        next_state <= IDLE;

                end if;

        when DECOMPRESS_START =>

                CLR_XMATCH_D <= '0';

                next_state <=   DECOMPRESS_START1;

        when DECOMPRESS_START1 =>

                next_state <=   DECOMPRESS_START2;

        when DECOMPRESS_START2 =>

                next_state <=   DECOMPRESS_INIT_BLOCKSIZE;

        when DECOMPRESS_INIT_BLOCKSIZE =>

                reg_STATUS_CDI <= x"00000006";

                RW_bit                                                  <= '0';

                CS_bit                                                  <= '0';

                ADDRESS_bit                                             <= to_bitvector (reg_ADDRESS);

                CONTROL_std                                             <= x"0000" & reg_BLOCKSIZE;

                next_state                                              <= DECOMPRESS_INIT_COMMAND;

        when DECOMPRESS_INIT_COMMAND =>

                reg_STATUS_CDI <= x"00000007";

                RW_bit                                                  <= '0';

                CS_bit                                                  <= '0';

                ADDRESS_bit                                             <= to_bitvector (reg_CONTROL);

                CONTROL_std                                             <= "0000000000000000" & "0100" & reg_THRESHOLD & "0000";

                next_state                                              <= DECOMPRESS_WAIT;

        -- Deompression wait if bus request DC is ready, and the FIFO of CoDMU is not empty (has data)

        when DECOMPRESS_WAIT =>

                reg_STATUS_CDI <= x"00000008";

                if BUS_REQUEST_DC_bit = '0' and empty_CODMU = '0' then

                        FIFO_read_signal <= '1';

                        next_state                      <= DECOMPRESS_WAIT_BUS_ACK_DC;

                else

                        next_state                      <= DECOMPRESS_WAIT;

                end if;

        -- Wait for 1 clock cycle of Bus Ack CU

        when DECOMPRESS_WAIT_BUS_ACK_DC =>

                next_state                      <= DECOMPRESS_WAIT_SEND;

        -- FIFO read signal has one delay clock cycle, before Wait DC is asserted

        when DECOMPRESS_WAIT_SEND =>

                if C_DATAIN_reg /= x"00000000" then

                        WAIT_DC_bit <= '1'; -- the WAIT_DC will not be triggered if the first word is 0

                end if;

                FIFO_read_signal <= '1';

                next_state <= DECOMPRESS_SEND_DATA;

        -- Send data from FIFO to Xmatch

        when DECOMPRESS_SEND_DATA =>

                WAIT_DC_bit <= '1';

                if C_DATAIN_reg = x"00000000" then

                        next_state <= DECOMPRESS_WAIT_FINISH_DC;

                elsif BUS_REQUEST_DC_bit = '1' then

                        next_state <= DECOMPRESS_WAIT_REQ_DC;

                else

                        FIFO_read_signal <= '1';

                        next_state <= DECOMPRESS_SEND_DATA;

                end if;

        -- Wait if Bus Request DC is availabe (0) again

        when DECOMPRESS_WAIT_REQ_DC =>

                if FINISHED_D_bit = '0' then

                        next_state                      <= DECOMPRESS_WAIT_INTERRUPT_REQUEST;

                elsif BUS_REQUEST_DC_bit = '0' then

                        next_state                      <= DECOMPRESS_WAIT_DC_SEND;

                else

                        next_state                      <= DECOMPRESS_WAIT_REQ_DC;

                end if;

        -- Read the first data goes out before read from FIFO again

        when DECOMPRESS_WAIT_DC_SEND =>

                WAIT_DC_bit <= '1';

                next_state      <= DECOMPRESS_SEND_DATA;

        -- The last tail was x"00000000", so WAIT_DC is asserted (with final compressed data) until BUS REQ DC has completed it's job

        when DECOMPRESS_WAIT_FINISH_DC =>

                WAIT_DC_bit <= '1';

                if BUS_REQUEST_DC_bit = '1' then

                        next_state <= DECOMPRESS_WAIT_REQ_DC;

                else

                        next_state <= DECOMPRESS_WAIT_FINISH_DC;

                end if;

        when DECOMPRESS_WAIT_INTERRUPT_REQUEST =>

                if INTERRUPT_REQUEST_bit = '0' then

                        INTERUPT_ACKNWLDGE_bit <= '0';

                        next_state              <= DECOMPRESS_WAIT_NEXT_PACKET;

--                      clr_CODMU               <= '0';

--                      next_state              <= IDLE;

                else

                        next_state              <= DECOMPRESS_WAIT_INTERRUPT_REQUEST;

                end if;

        when DECOMPRESS_WAIT_NEXT_PACKET =>

                if empty_CODMU = '0' then -- check if any packet left

                        CLR_XMATCH_D <= '0';

                        next_state <= DECOMPRESS_START; -- it will automatically starts Compressor Mode because there is still data available

                else

                        clr_CODMU       <= '0';

                        next_state <= IDLE;

                end if;

        when END_STATE =>

                if INTERRUPT_REQUEST_bit = '0' then

                        clr_CODMU               <= '0';

                        next_state              <= IDLE;

                else

                        next_state              <= END_STATE;

                end if;

  end case;

end process SM_COMB;

-- write compressed/decompressed data to write_buffer