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//////////////////////////////////////////////////////////////////////
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//// ////
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dinesha |
//// xSPI Interface Module ////
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//// ////
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//// This file is part of the xspi project ////
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//// https://opencores.org/projects/xspi ////
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//// ////
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//// Description ////
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//// xspi definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module xspi_cfg (
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mclk,
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reset_n,
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// Reg Bus Interface Signal
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reg_cs,
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reg_wr,
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reg_addr,
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reg_wdata,
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reg_be,
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// Outputs
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reg_rdata,
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reg_ack,
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// configuration signal
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cfg_tgt_sel ,
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cfg_op_req , // SPI operation request
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cfg_op_type , // SPI operation type
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cfg_transfer_size , // SPI transfer size
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cfg_sck_period , // sck clock period
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cfg_sck_cs_period , // cs setup/hold period
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cfg_cs_byte , // cs bit information
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cfg_datain , // data for transfer
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cfg_dataout , // data for received
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hware_op_done // operation done
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);
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input mclk;
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input reset_n;
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output [1:0] cfg_tgt_sel ;
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output cfg_op_req ; // SPI operation request
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output [1:0] cfg_op_type ; // SPI operation type
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output [1:0] cfg_transfer_size ; // SPI transfer size
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output [5:0] cfg_sck_period ; // sck clock period
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output [4:0] cfg_sck_cs_period ; // cs setup/hold period
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output [7:0] cfg_cs_byte ; // cs bit information
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output [31:0] cfg_datain ; // data for transfer
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input [31:0] cfg_dataout ; // data for received
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input hware_op_done ; // operation done
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//---------------------------------
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// Reg Bus Interface Signal
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//---------------------------------
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input reg_cs ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [3:0] reg_be ;
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// Outputs
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output [31:0] reg_rdata ;
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output reg_ack ;
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//-----------------------------------------------------------------------
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// Internal Wire Declarations
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//-----------------------------------------------------------------------
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wire sw_rd_en;
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wire sw_wr_en;
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wire [3:0] sw_addr ; // addressing 16 registers
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wire [3:0] wr_be ;
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reg [31:0] reg_rdata ;
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reg reg_ack ;
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wire [31:0] reg_0; // Software_Reg_0
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wire [31:0] reg_1; // Software-Reg_1
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wire [31:0] reg_2; // Software-Reg_2
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wire [31:0] reg_3 = 0; // Software-Reg_3
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wire [31:0] reg_4 = 0; // Software-Reg_4
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wire [31:0] reg_5 = 0; // Software-Reg_5
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wire [31:0] reg_6 = 0; // Software-Reg_6
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wire [31:0] reg_7 = 0; // Software-Reg_7
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wire [31:0] reg_8 = 0; // Software-Reg_8
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wire [31:0] reg_9 = 0; // Software-Reg_9
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wire [31:0] reg_10 = 0; // Software-Reg_10
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wire [31:0] reg_11 = 0; // Software-Reg_11
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wire [31:0] reg_12 = 0; // Software-Reg_12
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wire [31:0] reg_13 = 0; // Software-Reg_13
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wire [31:0] reg_14 = 0; // Software-Reg_14
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wire [31:0] reg_15 = 0; // Software-Reg_15
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reg [31:0] reg_out;
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//-----------------------------------------------------------------------
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// Main code starts here
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Internal Logic Starts here
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//-----------------------------------------------------------------------
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assign sw_addr = reg_addr [3:0];
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assign sw_rd_en = reg_cs & !reg_wr;
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assign sw_wr_en = reg_cs & reg_wr;
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assign wr_be = reg_be;
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//-----------------------------------------------------------------------
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// Read path mux
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//-----------------------------------------------------------------------
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always @ (posedge mclk or negedge reset_n)
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begin : preg_out_Seq
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if (reset_n == 1'b0)
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begin
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reg_rdata [31:0] <= 32'h0000_0000;
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reg_ack <= 1'b0;
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end
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else if (sw_rd_en && !reg_ack)
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begin
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reg_rdata [31:0] <= reg_out [31:0];
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reg_ack <= 1'b1;
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end
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else if (sw_wr_en && !reg_ack)
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reg_ack <= 1'b1;
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else
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begin
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reg_ack <= 1'b0;
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end
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end
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//-----------------------------------------------------------------------
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// register read enable and write enable decoding logic
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//-----------------------------------------------------------------------
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wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
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wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
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wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
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wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
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wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
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wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
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wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
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wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
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wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
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wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
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wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
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wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
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wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
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wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
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wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
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wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
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wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
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wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
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wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
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wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
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wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
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wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
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wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
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wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
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wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
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wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
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wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
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wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
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wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
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wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
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wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
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wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
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always @( *)
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begin : preg_sel_Com
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reg_out [31:0] = 32'd0;
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case (sw_addr [3:0])
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4'b0000 : reg_out [31:0] = reg_0 [31:0];
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4'b0001 : reg_out [31:0] = reg_1 [31:0];
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4'b0010 : reg_out [31:0] = reg_2 [31:0];
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4'b0011 : reg_out [31:0] = reg_3 [31:0];
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4'b0100 : reg_out [31:0] = reg_4 [31:0];
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4'b0101 : reg_out [31:0] = reg_5 [31:0];
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4'b0110 : reg_out [31:0] = reg_6 [31:0];
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4'b0111 : reg_out [31:0] = reg_7 [31:0];
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4'b1000 : reg_out [31:0] = reg_8 [31:0];
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4'b1001 : reg_out [31:0] = reg_9 [31:0];
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4'b1010 : reg_out [31:0] = reg_10 [31:0];
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4'b1011 : reg_out [31:0] = reg_11 [31:0];
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4'b1100 : reg_out [31:0] = reg_12 [31:0];
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4'b1101 : reg_out [31:0] = reg_13 [31:0];
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4'b1110 : reg_out [31:0] = reg_14 [31:0];
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4'b1111 : reg_out [31:0] = reg_15 [31:0];
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endcase
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end
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//-----------------------------------------------------------------------
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// Individual register assignments
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//-----------------------------------------------------------------------
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// Logic for Register 0 : SPI Control Register
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//-----------------------------------------------------------------------
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wire cfg_op_req = reg_0[31]; // cpu request
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wire [1:0] cfg_tgt_sel = reg_0[24:23]; // target chip select
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wire [1:0] cfg_op_type = reg_0[22:21]; // SPI operation type
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wire [1:0] cfg_transfer_size = reg_0[20:19]; // SPI transfer size
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wire [5:0] cfg_sck_period = reg_0[18:13]; // sck clock period
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wire [4:0] cfg_sck_cs_period = reg_0[12:8]; // cs setup/hold period
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wire [7:0] cfg_cs_byte = reg_0[7:0]; // cs bit information
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generic_register #(8,0 ) u_spi_ctrl_be0 (
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.we ({8{sw_wr_en_0 &
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wr_be[0] }} ),
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.data_in (reg_wdata[7:0] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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//List of Outs
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.data_out (reg_0[7:0] )
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);
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generic_register #(8,0 ) u_spi_ctrl_be1 (
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.we ({8{sw_wr_en_0 &
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wr_be[1] }} ),
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.data_in (reg_wdata[15:8] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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//List of Outs
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.data_out (reg_0[15:8] )
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);
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generic_register #(8,0 ) u_spi_ctrl_be2 (
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.we ({8{sw_wr_en_0 &
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wr_be[2] }} ),
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.data_in (reg_wdata[23:16] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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//List of Outs
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.data_out (reg_0[23:16] )
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);
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assign reg_0[30:24] = 7'h0;
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req_register #(0 ) u_spi_ctrl_req (
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.cpu_we ({sw_wr_en_0 &
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wr_be[3] } ),
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.cpu_req (reg_wdata[31] ),
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.hware_ack (hware_op_done ),
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.reset_n (reset_n ),
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.clk (mclk ),
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//List of Outs
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.data_out (reg_0[31] )
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);
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//-----------------------------------------------------------------------
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305 |
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// Logic for Register 1 : SPI Data In Register
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//-----------------------------------------------------------------------
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wire [31:0] cfg_datain = reg_1[31:0];
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generic_register #(8,0 ) u_spi_din_be0 (
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.we ({8{sw_wr_en_1 &
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wr_be[0] }} ),
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.data_in (reg_wdata[7:0] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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//List of Outs
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317 |
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.data_out (reg_1[7:0] )
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);
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319 |
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generic_register #(8,0 ) u_spi_din_be1 (
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.we ({8{sw_wr_en_1 &
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wr_be[1] }} ),
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.data_in (reg_wdata[15:8] ),
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.reset_n (reset_n ),
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.clk (mclk ),
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326 |
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//List of Outs
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328 |
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.data_out (reg_1[15:8] )
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329 |
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);
|
330 |
|
|
|
331 |
|
|
generic_register #(8,0 ) u_spi_din_be2 (
|
332 |
|
|
.we ({8{sw_wr_en_1 &
|
333 |
|
|
wr_be[2] }} ),
|
334 |
|
|
.data_in (reg_wdata[23:16] ),
|
335 |
|
|
.reset_n (reset_n ),
|
336 |
|
|
.clk (mclk ),
|
337 |
|
|
|
338 |
|
|
//List of Outs
|
339 |
|
|
.data_out (reg_1[23:16] )
|
340 |
|
|
);
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
generic_register #(8,0 ) u_spi_din_be3 (
|
344 |
|
|
.we ({8{sw_wr_en_1 &
|
345 |
|
|
wr_be[3] }} ),
|
346 |
|
|
.data_in (reg_wdata[31:24] ),
|
347 |
|
|
.reset_n (reset_n ),
|
348 |
|
|
.clk (mclk ),
|
349 |
|
|
|
350 |
|
|
//List of Outs
|
351 |
|
|
.data_out (reg_1[31:24] )
|
352 |
|
|
);
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
//-----------------------------------------------------------------------
|
356 |
|
|
// Logic for Register 2 : SPI Data output Register
|
357 |
|
|
//-----------------------------------------------------------------------
|
358 |
|
|
assign reg_2 = cfg_dataout;
|
359 |
|
|
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
endmodule
|