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[/] [xucpu/] [trunk/] [VHDL/] [ROM/] [tb_rom.vhdl] - Blame information for rev 2

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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY tb_rom IS
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END tb_rom;
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ARCHITECTURE behavior OF tb_rom IS
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  -- Component Declaration for the Unit Under Test (UUT)
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  COMPONENT driver
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    PORT(
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      clk : IN  STD_LOGIC;
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      led : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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      );
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  END COMPONENT;
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  --Inputs
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  SIGNAL clk : STD_LOGIC := '0';
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  --Outputs
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  SIGNAL led : STD_LOGIC_VECTOR(7 DOWNTO 0);
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  -- Clock period definitions
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  CONSTANT clk_period : TIME := 10 ns;
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BEGIN
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  -- Instantiate the Unit Under Test (UUT)
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  uut : driver PORT MAP (
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    clk => clk,
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    led => led
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    );
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  -- Clock process definitions
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  clk_process : PROCESS
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  BEGIN
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    clk <= '0';
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    WAIT FOR clk_period/2;
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    clk <= '1';
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    WAIT FOR clk_period/2;
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  END PROCESS;
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  -- Stimulus process
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  stim_proc : PROCESS
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  BEGIN
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    -- hold reset state for 20 ns.
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    WAIT FOR 20 ns;
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    WAIT;
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  END PROCESS;
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END;

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