OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [VHDL/] [clock/] [test_clock.vhdl] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 lcdsgmtr
-- Copyright 2015, Jürgen Defurne
2
--
3
-- This file is part of the Experimental Unstable CPU System.
4
--
5
-- The Experimental Unstable CPU System Is free software: you can redistribute
6
-- it and/or modify it under the terms of the GNU Lesser General Public License
7
-- as published by the Free Software Foundation, either version 3 of the
8
-- License, or (at your option) any later version.
9
--
10
-- The Experimental Unstable CPU System is distributed in the hope that it will
11
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
12
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
13
-- General Public License for more details.
14
--
15
-- You should have received a copy of the GNU Lesser General Public License
16
-- along with Experimental Unstable CPU System. If not, see
17
-- http://www.gnu.org/licenses/lgpl.txt.
18
 
19
 
20
LIBRARY ieee;
21
USE ieee.std_logic_1164.ALL;
22
 
23
-- Uncomment the following library declaration if using
24
-- arithmetic functions with Signed or Unsigned values
25
--USE ieee.numeric_std.ALL;
26
 
27
ENTITY test_clock IS
28
END test_clock;
29
 
30
ARCHITECTURE behavior OF test_clock IS
31
 
32
  -- Component Declaration for the Unit Under Test (UUT)
33
 
34
  COMPONENT clock
35
    PORT(
36
      clock_in     : IN  STD_LOGIC;
37
      clock_out    : OUT STD_LOGIC;
38
      clock_locked : OUT STD_LOGIC
39
      );
40
  END COMPONENT;
41
 
42
 
43
  --Inputs
44
  SIGNAL clock_in : STD_LOGIC := '0';
45
 
46
  --Outputs
47
  SIGNAL clock_out    : STD_LOGIC;
48
  SIGNAL clock_locked : STD_LOGIC;
49
 
50
  -- Clock period definitions
51
  CONSTANT clock_in_period     : TIME := 10 ns;
52
  CONSTANT clock_out_period    : TIME := 10 ns;
53
  CONSTANT clock_locked_period : TIME := 10 ns;
54
 
55
BEGIN
56
 
57
  -- Instantiate the Unit Under Test (UUT)
58
  uut : clock PORT MAP (
59
    clock_in     => clock_in,
60
    clock_out    => clock_out,
61
    clock_locked => clock_locked
62
    );
63
 
64
  -- Clock process definitions
65
  clock_in_process : PROCESS
66
  BEGIN
67
    clock_in <= '0';
68
    WAIT FOR clock_in_period/2;
69
    clock_in <= '1';
70
    WAIT FOR clock_in_period/2;
71
  END PROCESS;
72
 
73
  -- Stimulus process
74
  stim_proc : PROCESS
75
  BEGIN
76
    -- hold reset state for 100 ns.
77
    WAIT FOR 100 ns;
78
 
79
    WAIT FOR clock_in_period*10;
80
 
81
    -- insert stimulus here 
82
 
83
    WAIT;
84
  END PROCESS;
85
 
86
END;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.