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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY ct IS
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PORT (reset : IN STD_LOGIC;
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clock : IN STD_LOGIC;
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ir_in : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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reg_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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reg_b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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op_sel : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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reg_input : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
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reg_write : OUT STD_LOGIC;
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pc_input : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
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addr_source : OUT STD_LOGIC;
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wr : OUT STD_LOGIC;
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rd : OUT STD_LOGIC;
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zero : IN STD_LOGIC;
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n_zero : IN STD_LOGIC);
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END ct;
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ARCHITECTURE Behavioral OF ct IS
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TYPE ctr_state IS (one, two, three, four, five, six, seven, eight);
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SIGNAL ir : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL cr_reg_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL cr_reg_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL cr_op_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL cr_reg_input : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL cr_reg_write : STD_LOGIC;
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SIGNAL cr_pc_input : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL cr_addr_source : STD_LOGIC;
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SIGNAL cr_wr : STD_LOGIC;
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SIGNAL cr_rd : STD_LOGIC;
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SIGNAL cr_state : ctr_state;
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SIGNAL nx_reg_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL nx_reg_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL nx_op_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL nx_reg_input : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL nx_reg_write : STD_LOGIC;
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SIGNAL nx_pc_input : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL nx_addr_source : STD_LOGIC;
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SIGNAL nx_wr : STD_LOGIC;
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SIGNAL nx_rd : STD_LOGIC;
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SIGNAL nx_state : ctr_state;
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BEGIN
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-- purpose: This is the state controller register
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-- type : sequential
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-- inputs : clock, reset, zero,n_zero, next_state
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-- outputs: cr_reg_a,cr_reg_b,cr_op_sel,cr_reg_input,cr_reg_write,cr_pc_input,cr_addr_source,cr_wr,cr_rd
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control_out : PROCESS (clock, reset)
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BEGIN -- PROCESS control_out
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IF reset = '0' THEN -- asynchronous reset (active low)
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cr_reg_a <= "0000";
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cr_reg_b <= "0000";
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cr_op_sel <= "0000";
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cr_reg_input <= "00";
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cr_reg_write <= '0';
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cr_pc_input <= "00";
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cr_addr_source <= '0';
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cr_state <= one;
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ELSIF rising_edge(clock) THEN -- rising clock edge
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cr_reg_a <= nx_reg_a;
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cr_reg_b <= nx_reg_b;
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cr_op_sel <= nx_op_sel;
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cr_reg_input <= nx_reg_input;
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cr_reg_write <= nx_reg_write;
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cr_pc_input <= nx_pc_input;
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cr_addr_source <= nx_addr_source;
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cr_state <= nx_state;
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END IF;
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END PROCESS control_out;
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-- purpose: Compute the next state and outputs from the current state
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-- type : combinational
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-- inputs : state, zero, n_zero
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-- outputs: nx_reg_a,nx_reg_b,nx_op_sel,nx_reg_input,nx_reg_write,nx_pc_inpue,nx_addr_source,nx_state
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next_control : PROCESS (cr_state, zero, n_zero)
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BEGIN -- PROCESS next_control
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nx_reg_a <= "0000";
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nx_reg_b <= "0000";
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nx_op_sel <= "0000";
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nx_reg_input <= "00";
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nx_reg_write <= '0';
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nx_pc_input <= "00";
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nx_addr_source <= '0';
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nx_state <= one;
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CASE cr_state IS
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WHEN one =>
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nx_state <= two;
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WHEN two =>
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nx_state <= three;
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WHEN three =>
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nx_state <= four;
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WHEN four =>
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nx_state <= five;
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WHEN five =>
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nx_state <= six;
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WHEN six =>
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nx_state <= seven;
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WHEN seven =>
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nx_state <= one;
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WHEN eight =>
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nx_state <= one;
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END CASE;
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END PROCESS next_control;
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reg_a <= cr_reg_a;
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reg_b <= cr_reg_b;
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op_sel <= cr_op_sel;
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reg_input <= cr_reg_input;
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reg_write <= cr_reg_write;
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pc_input <= cr_pc_input;
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addr_source <= cr_addr_source;
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wr <= cr_wr;
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rd <= cr_rd;
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END Behavioral;
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