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[/] [xucpu/] [trunk/] [VHDL/] [mux8to1/] [mux4to1.vhdl] - Blame information for rev 2

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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY unisim;
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USE unisim.vcomponents.ALL;
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ENTITY mux8to1 IS
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  GENERIC (
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    width : NATURAL := 1);
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  PORT (
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    S0  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S1  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S2  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S3  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S4  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S5  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S6  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    S7  : IN  STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
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    sel : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
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    Y   : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0));
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END mux8to1;
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--ARCHITECTURE component_based OF mux4to1 IS
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--BEGIN
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--  MUX1 :
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--  FOR i IN width - 1 DOWNTO 0 GENERATE
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--    MUX : LUT6
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--      GENERIC MAP (INIT => X"FF00F0F0CCCCAAAA")
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--      PORT MAP(I0 => S0(i),
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--               I1 => S1(i),
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--               I2 => S2(i),
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--               I3 => S3(i),
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--               I4 => sel(0),
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--               I5 => sel(1),
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--               O  => Y(i));
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--  END GENERATE MUX1;
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--END component_based;
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ARCHITECTURE Behavioral OF mux8to1 IS
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BEGIN  -- Behavioral
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  WITH sel SELECT
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    Y <=
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    S0 WHEN "000",
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    S1 WHEN "001",
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    S2 WHEN "010",
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    S3 WHEN "011",
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    S4 WHEN "100",
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    S5 WHEN "101",
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    S6 WHEN "110",
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    S7 WHEN "111";
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END Behavioral;

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