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[/] [xucpu/] [trunk/] [VHDL/] [pipeline/] [memory_processor-mealy.vhdl] - Blame information for rev 3

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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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ARCHITECTURE mealy OF memory_processor IS
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  TYPE state IS (S0, S1, S2, S3);
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  SIGNAL current_state : state;
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  SIGNAL next_state    : state;
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BEGIN  -- ARCHITECTURE mealy
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  -- Mealy machine input combinational logic: next state
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  PROCESS (current_state, FULL)
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  BEGIN
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    CASE current_state IS
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      WHEN S0 =>
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        IF FULL = '0' THEN
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          next_state <= S0;
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        ELSE
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          next_state <= S1;
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        END IF;
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      WHEN S1 =>
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        next_state <= S2;
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      WHEN S2 =>
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        next_state <= S3;
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      WHEN S3 =>
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        next_state <= S3;
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    END CASE;
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  END PROCESS;
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  -- Mealy machine sequential state logic
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  PROCESS (CLK, RST)
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  BEGIN
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    IF rising_edge(CLK) THEN
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      IF RST = '1' THEN
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        current_state <= S0;
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      ELSE
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        current_state <= next_state;
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      END IF;
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    END IF;
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  END PROCESS;
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  -- Mealy machine output combinational logic
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  PROCESS (current_state, FULL)
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  BEGIN
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    CASE current_state IS
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      WHEN S0 =>
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        IF full = '0' THEN
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          PULL <= '0';
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        ELSE
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          PULL <= '1';
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        END IF;
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      WHEN S1 =>
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        PULL <= '0';
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      WHEN S2 =>
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        PULL <= '0';
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      WHEN S3 =>
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        PULL <= '0';
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    END CASE;
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  END PROCESS;
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END ARCHITECTURE mealy;

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