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[/] [xucpu/] [trunk/] [VHDL/] [pipeline/] [pipeline_reg.vhdl] - Blame information for rev 2

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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY pipeline_reg IS
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  PORT (
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    D   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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    Q   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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    CLK : IN  STD_LOGIC;
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    EN  : IN  STD_LOGIC);
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END ENTITY pipeline_reg;
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ARCHITECTURE Behavioral OF pipeline_reg IS
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BEGIN  -- ARCHITECTURE Behavioral
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  PROCESS (CLK) IS
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  BEGIN  -- PROCESS
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    IF rising_edge(CLK) THEN
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      IF EN = '1' THEN
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        Q <= D;
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      END IF;
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    END IF;
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  END PROCESS;
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END ARCHITECTURE Behavioral;

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