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[/] [xucpu/] [trunk/] [VHDL/] [queue/] [queue.vhdl] - Blame information for rev 2

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1 2 lcdsgmtr 
-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY queue IS
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  PORT (
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    data_in  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
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    data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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    clock    : IN  STD_LOGIC;
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    wr       : IN  STD_LOGIC;
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    sh       : IN  STD_LOGIC;
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    reset    : IN  STD_LOGIC);
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END queue;
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ARCHITECTURE Behavioral OF queue IS
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  -- Datapath declarations
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  TYPE queue_t IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
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  SIGNAL queue : queue_t;
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  -- Control path declarations
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  SUBTYPE cntr_t IS INTEGER RANGE 0 TO 4;
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  SIGNAL i      : cntr_t := 0;
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  SIGNAL i_next : cntr_t := 0;
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BEGIN  -- Behavioral
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  -- Datapath
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  -- Control path
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  -- purpose: Control the queue
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  -- type   : sequential
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  -- inputs : clock, reset, wr
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  -- outputs:
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  control : PROCESS (clock, reset)
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  BEGIN  -- PROCESS control
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    IF rising_edge(clock) THEN          -- rising clock edge
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      IF reset = '1' THEN               -- synchronous reset (active high)
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        i <= 0;
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      ELSE
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        i <= i_next;
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      END IF;
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    END IF;
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  END PROCESS control;
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  -- purpose: Implement the queue
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  -- type   : sequential
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  -- inputs : clock, reset, wr, sh
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  -- outputs: out
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  data: PROCESS (clock, reset)
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  BEGIN  -- PROCESS data
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    IF rising_edge(clock) THEN  -- rising clock edge
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      CASE i IS
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        WHEN 0 =>
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          IF wr = '1' AND sh = '0' THEN
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= data_in;
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            i_next   <= 1;
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          ELSIF wr = '0' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 0;
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          ELSIF wr = '1' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 0;
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          ELSE
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 0;
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          END IF;
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        WHEN 1 =>
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          IF wr = '1' AND sh = '0' THEN
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= data_in;
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            queue(0) <= queue(0);
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            i_next   <= 2;
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          ELSIF wr = '0' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 0;
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          ELSIF wr = '1' AND sh = '1' THEN
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= data_in;
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            i_next   <= 1;
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          ELSE
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 1;
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          END IF;
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        WHEN 2 =>
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          IF wr = '1' AND sh = '0' THEN
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            queue(3) <= queue(3);
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            queue(2) <= data_in;
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 3;
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          ELSIF wr = '0' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 1;
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          ELSIF wr = '1' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= data_in;
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            queue(0) <= queue(1);
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            i_next   <= 2;
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          ELSE
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 2;
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          END IF;
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        WHEN 3 =>
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          IF wr = '1' AND sh = '0' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 4;
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          ELSIF wr = '0' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 2;
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          ELSIF wr = '1' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= data_in;
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 3;
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          ELSE
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 3;
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          END IF;
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        WHEN 4 =>
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          IF wr = '1' AND sh = '0' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 4;
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          ELSIF wr = '0' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 3;
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          ELSIF wr = '1' AND sh = '1' THEN
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            queue(3) <= data_in;
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            queue(2) <= queue(3);
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            queue(1) <= queue(2);
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            queue(0) <= queue(1);
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            i_next   <= 4;
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          ELSE
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            queue(3) <= queue(3);
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            queue(2) <= queue(2);
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            queue(1) <= queue(1);
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            queue(0) <= queue(0);
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            i_next   <= 4;
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          END IF;
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      END CASE;
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    END IF;
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  END PROCESS data;
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  data_out <= queue(0);
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END Behavioral;

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