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[/] [xucpu/] [trunk/] [VHDL/] [registers/] [control.vhdl] - Blame information for rev 39

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1 2 lcdsgmtr 
-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY uctrl IS
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  PORT (
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    CLK    : IN  STD_LOGIC;
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    RST    : IN  STD_LOGIC;
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    RF_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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    A1     : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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    A2     : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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    LO_EN  : OUT STD_LOGIC;
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    RO_EN  : OUT STD_LOGIC;
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    OPCODE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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    WR     : OUT STD_LOGIC);
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END ENTITY uctrl;
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ARCHITECTURE Mealy OF uctrl IS
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  TYPE state IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9);
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  SIGNAL CURR_STATE : state;
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  SIGNAL NEXT_STATE : state;
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BEGIN  -- ARCHITECTURE Mealy
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  -- Next state logic
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  PROCESS (CURR_STATE)
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  BEGIN
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    CASE CURR_STATE IS
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      WHEN S0 =>
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        NEXT_STATE <= S1;
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      WHEN S1 =>
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        NEXT_STATE <= S2;
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      WHEN S2 =>
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        NEXT_STATE <= S3;
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      WHEN S3 =>
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        NEXT_STATE <= S4;
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      WHEN S4 =>
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        NEXT_STATE <= S5;
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      WHEN S5 =>
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        NEXT_STATE <= S6;
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      WHEN S6 =>
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        NEXT_STATE <= S7;
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      WHEN S7 =>
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        NEXT_STATE <= S8;
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      WHEN S8 =>
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        NEXT_STATE <= S9;
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      WHEN S9 =>
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        NEXT_STATE <= S9;
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    END CASE;
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  END PROCESS;
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  -- State logic
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  PROCESS (CLK, RST)
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  BEGIN
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    IF rising_edge(CLK) THEN
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      IF RST = '0' THEN
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        CURR_STATE <= NEXT_STATE;
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      ELSE
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        CURR_STATE <= S0;
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      END IF;
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    END IF;
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  END PROCESS;
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  -- Output logic
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  PROCESS (CURR_STATE)
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  BEGIN
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    RF_SEL <= "00";
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    CASE CURR_STATE IS
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      WHEN S0 =>
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        A1     <= "00";
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "00";
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        WR     <= '0';
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      WHEN S1 =>
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        A1     <= "00"; -- LD REG 0 with 0
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "00";
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        WR     <= '1';
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      WHEN S2 =>
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        A1     <= "01"; -- LD REG 1 with 0
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "00";
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        WR     <= '1';
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      WHEN S3 =>
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        A1     <= "00";
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        A2     <= "00";
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        LO_EN  <= '1'; -- LD Left op with REG 0
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        RO_EN  <= '0';
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        OPCODE <= "00";
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        WR     <= '0';
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      WHEN S4 =>
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        A1     <= "00"; -- Store result in REG 0
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "10";
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        WR     <= '1';
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      WHEN S5 =>
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        A1     <= "01";
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        A2     <= "00";
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        LO_EN  <= '1'; -- LD Left op with REG 1
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        RO_EN  <= '0';
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        OPCODE <= "00";
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        WR     <= '0';
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      WHEN S6 =>
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        A1     <= "01"; -- Store result in REG 1
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "10";
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        WR     <= '1';
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      WHEN S7 =>
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        A1     <= "00";
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        A2     <= "01";
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        LO_EN  <= '1';
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        RO_EN  <= '1';
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        OPCODE <= "00";
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        WR     <= '0';
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      WHEN S8 =>
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        A1     <= "00";
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "01";
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        WR     <= '1';
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      WHEN S9 =>
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        A1     <= "00";
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        A2     <= "00";
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        LO_EN  <= '0';
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        RO_EN  <= '0';
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        OPCODE <= "00";
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        WR     <= '0';
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    END CASE;
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  END PROCESS;
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END ARCHITECTURE Mealy;

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