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-- Copyright 2015, Jürgen Defurne

--

-- This file is part of the Experimental Unstable CPU System.

--

-- The Experimental Unstable CPU System Is free software: you can redistribute

-- it and/or modify it under the terms of the GNU Lesser General Public License

-- as published by the Free Software Foundation, either version 3 of the

-- License, or (at your option) any later version.

--

-- The Experimental Unstable CPU System is distributed in the hope that it will

-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser

-- General Public License for more details.

--

-- You should have received a copy of the GNU Lesser General Public License

-- along with Experimental Unstable CPU System. If not, see

-- http://www.gnu.org/licenses/lgpl.txt.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY tb_flipflop IS

END tb_flipflop;

ARCHITECTURE behavior OF tb_flipflop IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT flipflop

    PORT(

         clock : IN  std_logic;

         sig : OUT  std_logic

        );

    END COMPONENT;

   --Inputs

   signal clock : std_logic := '0';

        --Outputs

   signal sig : std_logic;

   -- Clock period definitions

   constant clock_period : time := 2.5 ns;

BEGIN

        -- Instantiate the Unit Under Test (UUT)

   uut: flipflop PORT MAP (

          clock => clock,

          sig => sig

        );

   -- Clock process definitions

   clock_process :process

   begin

                clock <= '0';

                wait for clock_period/2;

                clock <= '1';

                wait for clock_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin

      -- hold reset state for 100 ns.

      wait for 100 ns;

      wait for clock_period*10;

      -- insert stimulus here 

      wait;

   end process;

END;