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-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY ieee;
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USE ieee.STD_LOGIC_1164.ALL;
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USE ieee.NUMERIC_STD.ALL;
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ENTITY alu IS
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GENERIC(
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w_data : NATURAL RANGE 1 TO 32 := 16);
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PORT(
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op : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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B : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
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FUNCTION alu_add (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_add(
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN -- alu_add
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B));
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END alu_add;
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FUNCTION alu_sub (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_sub(
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
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SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN -- alu_sub
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B));
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END alu_sub;
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FUNCTION alu_inc (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_inc (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) + 1);
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END alu_inc;
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FUNCTION alu_dec (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION alu_dec (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN STD_LOGIC_VECTOR(UNSIGNED(A) - 1);
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END alu_dec;
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FUNCTION shift_left (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION shift_left (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN STD_LOGIC_VECTOR(shift_left(UNSIGNED(A), 1));
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END shift_left;
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FUNCTION shift_right (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR;
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FUNCTION shift_right (
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SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
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RETURN STD_LOGIC_VECTOR IS
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BEGIN
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RETURN STD_LOGIC_VECTOR(shift_right(UNSIGNED(A), 1));
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END shift_right;
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END ENTITY alu;
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ARCHITECTURE Behavioral OF alu IS
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CONSTANT ZERO : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)
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:= STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data));
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CONSTANT ONE : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)
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:= STD_LOGIC_VECTOR(TO_UNSIGNED(1, w_data));
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BEGIN -- ARCHITECTURE Behavioral
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WITH op SELECT
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y <=
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alu_inc(A) WHEN "0000",
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alu_dec(A) WHEN "0001",
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ZERO WHEN "0010", -- Place holder
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ONE WHEN "0011", -- Place holder
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B WHEN "0100",
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A WHEN "0101", -- Place holder
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A WHEN "0110", -- Place holder
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alu_add(A, B) WHEN "0111",
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alu_sub(A, B) WHEN "1000",
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A WHEN "1001", -- Place holder
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A AND B WHEN "1010",
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A OR B WHEN "1011",
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A XOR B WHEN "1100",
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NOT A WHEN "1101",
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shift_left(A) WHEN "1110",
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shift_right(A) WHEN "1111",
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A WHEN OTHERS;
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END ARCHITECTURE Behavioral;
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