OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [ALU/] [logic.vhdl] - Blame information for rev 20

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 lcdsgmtr
LIBRARY IEEE;
2
USE IEEE.STD_LOGIC_1164.ALL;
3
USE IEEE.numeric_std.ALL;
4
 
5
ENTITY logic IS
6
 
7
  GENERIC (
8
    w_data : NATURAL RANGE 1 TO 32 := 16);
9
 
10
  PORT (
11
    A  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
12
    B  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
13
    OP : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
14
    Y  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
15
 
16
END logic;
17
 
18
ARCHITECTURE Behavioral OF logic IS
19
 
20
  CONSTANT zero : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0) := (OTHERS => '0');
21
 
22
BEGIN  -- Behavioral
23
 
24
  WITH OP SELECT
25
    Y <=
26
    A       WHEN "000",
27
    NOT A   WHEN "001",
28
    A AND B WHEN "010",
29
    A OR B  WHEN "011",
30
    A XOR B WHEN "100",
31
    B       WHEN "101",
32
    zero    WHEN "110",
33
    zero    WHEN "111",
34
    zero    WHEN OTHERS;
35
 
36
END Behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.