Subversion Repositories xucpu

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE work.hexio.ALL;

ENTITY RAM_GENERIC IS

  -- Memory component based upon Xilinx Spartan-6 block RAM

  -- Maximum capacity is 16k words

  -- This component can be initialised by passing a file name as a generic

  -- parameter.

  GENERIC (

    filename : STRING                := "";

    w_data   : NATURAL RANGE 1 TO 32 := 16;

    w_addr   : NATURAL RANGE 8 TO 14 := 10);

  PORT (

    clk : IN  STD_LOGIC;

    we  : IN  STD_LOGIC;

    a1  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Data port address

    a2  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Instruction port address

    d1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port input

    q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port output

    q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output

END RAM_GENERIC;

ARCHITECTURE Behavioral OF RAM_GENERIC IS

  COMPONENT generic_memory_block IS

    -- Memory component based upon Xilinx Spartan-6 block RAM

    -- Maximum capacity is 16k words

    -- This component can be initialised by passing a file name as a generic

    -- parameter.

    GENERIC (

      init_data : cstr_array_type;

      w_data    : NATURAL RANGE 1 TO 32 := 16;

      w_addr    : NATURAL RANGE 8 TO 14 := 10);

    PORT (

      clk : IN  STD_LOGIC;

      we  : IN  STD_LOGIC;

      a1  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Data port address

      a2  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Instruction port address

      d1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port input

      q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port output

      q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output

  END COMPONENT generic_memory_block;

BEGIN  -- Behavioral

  MEM1 : generic_memory_block

    GENERIC MAP (

      init_data => init_cstr(2**w_addr, filename),

      w_data    => w_data,

      w_addr    => w_addr)

    PORT MAP (

      clk => clk,

      we  => we,

      a1  => a1,

      a2  => a2,

      d1  => d1,

      q1  => q1,

      q2  => q2);

END Behavioral;