URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [multiplexer/] [MUX.vhdl] - Blame information for rev 5

Details | Compare with Previous | View Log


-- Copyright 2015, J�rgen Defurne
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
PACKAGE mux_parts IS
 
  COMPONENT mux2to1 IS
 
    GENERIC (
      w_data : NATURAL RANGE 1 TO 32 := 16);
 
    PORT (
      SEL : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
      S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
  END COMPONENT mux2to1;
 
  COMPONENT mux4to1 IS
 
    GENERIC (
      w_data : NATURAL RANGE 1 TO 32 := 16);
 
    PORT (
      SEL : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
      S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
  END COMPONENT mux4to1;
 
  COMPONENT mux8to1 IS
 
    GENERIC (
      w_data : NATURAL RANGE 1 TO 32 := 16);
 
    PORT (
      SEL : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
      S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S4  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S5  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S6  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S7  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
  END COMPONENT mux8to1;
 
  COMPONENT mux16to1 IS
 
    GENERIC (
      w_data : NATURAL RANGE 1 TO 32 := 16);
 
    PORT (
      SEL : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
      S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S4  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S5  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S6  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S7  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S8  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S9  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S10 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S11 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S12 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S13 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S14 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      S15 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
      Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
  END COMPONENT mux16to1;
 
END mux_parts;
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY mux2to1 IS
 
  GENERIC (
    w_data : NATURAL RANGE 1 TO 32 := 16);
 
  PORT (
    SEL : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
    S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
END mux2to1;
 
ARCHITECTURE Behavioral OF mux2to1 IS
 
BEGIN  -- Behavioral
 
  WITH SEL SELECT
    Y <=
    S0 WHEN "0",
    S1 WHEN "1",
    S0 WHEN OTHERS;
 
END Behavioral;
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY mux4to1 IS
 
  GENERIC (
    w_data : NATURAL RANGE 1 TO 32 := 16);
 
  PORT (
    SEL : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
    S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
END mux4to1;
 
ARCHITECTURE Behavioral OF mux4to1 IS
 
BEGIN  -- Behavioral
 
  WITH SEL SELECT
    Y <=
    S0 WHEN "00",
    S1 WHEN "01",
    S2 WHEN "10",
    S3 WHEN "11",
    S0 WHEN OTHERS;
 
END Behavioral;
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY mux8to1 IS
 
  GENERIC (
    w_data : NATURAL RANGE 1 TO 32 := 16);
 
  PORT (
    SEL : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
    S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S4  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S5  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S6  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S7  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
END mux8to1;
 
ARCHITECTURE Behavioral OF mux8to1 IS
 
BEGIN  -- Behavioral
 
  WITH SEL SELECT
    Y <=
    S0 WHEN "000",
    S1 WHEN "001",
    S2 WHEN "010",
    S3 WHEN "011",
    S4 WHEN "100",
    S5 WHEN "101",
    S6 WHEN "110",
    S7 WHEN "111",
    S0 WHEN OTHERS;
 
END Behavioral;
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY mux16to1 IS
 
  GENERIC (
    w_data : NATURAL RANGE 1 TO 32 := 16);
 
  PORT (
    SEL : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
    S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S4  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S5  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S6  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S7  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S8  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S9  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S10 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S11 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S12 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S13 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S14 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S15 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
END mux16to1;
 
ARCHITECTURE Behavioral OF mux16to1 IS
 
BEGIN  -- Behavioral
 
  WITH SEL SELECT
    Y <=
    S0  WHEN "0000",
    S1  WHEN "0001",
    S2  WHEN "0010",
    S3  WHEN "0011",
    S4  WHEN "0100",
    S5  WHEN "0101",
    S6  WHEN "0110",
    S7  WHEN "0111",
    S8  WHEN "1000",
    S9  WHEN "1001",
    S10 WHEN "1010",
    S11 WHEN "1011",
    S12 WHEN "1100",
    S13 WHEN "1101",
    S14 WHEN "1110",
    S15 WHEN "1111",
    S0  WHEN OTHERS;
 
END Behavioral;
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.mux_parts.ALL;
 
ENTITY mux32to1 IS
 
  GENERIC (
    w_data : NATURAL RANGE 1 TO 32 := 16);
 
  PORT (
    SEL : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
    S0  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S2  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S3  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S4  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S5  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S6  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S7  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S8  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S9  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S10 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S11 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S12 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S13 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S14 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S15 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S16 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S17 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S18 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S19 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S20 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S21 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S22 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S23 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S24 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S25 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S26 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S27 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S28 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S29 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S30 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    S31 : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
    Y   : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
END mux32to1;
 
ARCHITECTURE Behavioral OF mux32to1 IS
 
  SIGNAL M1_Y : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
  SIGNAL M2_Y : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
 
  SIGNAL sub_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL out_sel : STD_LOGIC_VECTOR(0 DOWNTO 0);
 
BEGIN  -- Behavioral
 
  sub_sel <= SEL(3 DOWNTO 0);
  out_sel <= SEL(4 DOWNTO 4);
 
  M1 : mux16to1
    GENERIC MAP (
      w_data => w_data)
    PORT MAP (
      SEL => sub_sel,
      S0  => S0,
      S1  => S1,
      S2  => S2,
      S3  => S3,
      S4  => S4,
      S5  => S5,
      S6  => S6,
      S7  => S7,
      S8  => S8,
      S9  => S9,
      S10 => S10,
      S11 => S11,
      S12 => S12,
      S13 => S13,
      S14 => S14,
      S15 => S15,
      Y   => M1_Y);
 
  M2 : mux16to1
    GENERIC MAP (
      w_data => w_data)
    PORT MAP (
      SEL => sub_sel,
      S0  => S16,
      S1  => S17,
      S2  => S18,
      S3  => S19,
      S4  => S20,
      S5  => S21,
      S6  => S22,
      S7  => S23,
      S8  => S24,
      S9  => S25,
      S10 => S26,
      S11 => S27,
      S12 => S28,
      S13 => S29,
      S14 => S30,
      S15 => S31,
      Y   => M2_Y);
 
  M3 : mux2to1
    GENERIC MAP (
      w_data => w_data)
    PORT MAP (
      SEL => out_sel,
      S0  => M1_Y,
      S1  => M2_Y,
      Y   => Y);
 
END Behavioral;

Browse

Tools

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [multiplexer/] [MUX.vhdl] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	lcdsgmtr	`-- Copyright 2015, J�rgen Defurne`
2			`--`
3			`-- This file is part of the Experimental Unstable CPU System.`
4			`--`
5			`-- The Experimental Unstable CPU System Is free software: you can redistribute`
6			`-- it and/or modify it under the terms of the GNU Lesser General Public License`
7			`-- as published by the Free Software Foundation, either version 3 of the`
8			`-- License, or (at your option) any later version.`
9			`--`
10			`-- The Experimental Unstable CPU System is distributed in the hope that it will`
11			`-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser`
13			`-- General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU Lesser General Public License`
16			`-- along with Experimental Unstable CPU System. If not, see`
17			`-- http://www.gnu.org/licenses/lgpl.txt.`
18
19
20			`LIBRARY IEEE;`
21			`USE IEEE.STD_LOGIC_1164.ALL;`
22
23			`PACKAGE mux_parts IS`
24
25			`COMPONENT mux2to1 IS`
26
27			`GENERIC (`
28			`w_data : NATURAL RANGE 1 TO 32 := 16);`
29
30			`PORT (`
31			`SEL : IN STD_LOGIC_VECTOR(0 DOWNTO 0);`
32			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
33			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
34			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
35
36			`END COMPONENT mux2to1;`
37
38			`COMPONENT mux4to1 IS`
39
40			`GENERIC (`
41			`w_data : NATURAL RANGE 1 TO 32 := 16);`
42
43			`PORT (`
44			`SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);`
45			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
46			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
47			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
48			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
49			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
50
51			`END COMPONENT mux4to1;`
52
53			`COMPONENT mux8to1 IS`
54
55			`GENERIC (`
56			`w_data : NATURAL RANGE 1 TO 32 := 16);`
57
58			`PORT (`
59			`SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);`
60			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
61			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
62			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
63			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
64			`S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
65			`S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
66			`S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
67			`S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
68			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
69
70			`END COMPONENT mux8to1;`
71
72			`COMPONENT mux16to1 IS`
73
74			`GENERIC (`
75			`w_data : NATURAL RANGE 1 TO 32 := 16);`
76
77			`PORT (`
78			`SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);`
79			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
80			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
81			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
82			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
83			`S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
84			`S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
85			`S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
86			`S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
87			`S8 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
88			`S9 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
89			`S10 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
90			`S11 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
91			`S12 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
92			`S13 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
93			`S14 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
94			`S15 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
95			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
96
97			`END COMPONENT mux16to1;`
98
99			`END mux_parts;`
100
101			`LIBRARY IEEE;`
102			`USE IEEE.std_logic_1164.ALL;`
103			`USE ieee.numeric_std.ALL;`
104
105			`ENTITY mux2to1 IS`
106
107			`GENERIC (`
108			`w_data : NATURAL RANGE 1 TO 32 := 16);`
109
110			`PORT (`
111			`SEL : IN STD_LOGIC_VECTOR(0 DOWNTO 0);`
112			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
113			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
114			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
115
116			`END mux2to1;`
117
118			`ARCHITECTURE Behavioral OF mux2to1 IS`
119
120			`BEGIN -- Behavioral`
121
122			`WITH SEL SELECT`
123			`Y <=`
124			`S0 WHEN "0",`
125			`S1 WHEN "1",`
126			`S0 WHEN OTHERS;`
127
128			`END Behavioral;`
129
130			`LIBRARY IEEE;`
131			`USE IEEE.std_logic_1164.ALL;`
132			`USE ieee.numeric_std.ALL;`
133
134			`ENTITY mux4to1 IS`
135
136			`GENERIC (`
137			`w_data : NATURAL RANGE 1 TO 32 := 16);`
138
139			`PORT (`
140			`SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);`
141			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
142			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
143			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
144			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
145			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
146
147			`END mux4to1;`
148
149			`ARCHITECTURE Behavioral OF mux4to1 IS`
150
151			`BEGIN -- Behavioral`
152
153			`WITH SEL SELECT`
154			`Y <=`
155			`S0 WHEN "00",`
156			`S1 WHEN "01",`
157			`S2 WHEN "10",`
158			`S3 WHEN "11",`
159			`S0 WHEN OTHERS;`
160
161			`END Behavioral;`
162
163			`LIBRARY IEEE;`
164			`USE IEEE.std_logic_1164.ALL;`
165			`USE ieee.numeric_std.ALL;`
166
167			`ENTITY mux8to1 IS`
168
169			`GENERIC (`
170			`w_data : NATURAL RANGE 1 TO 32 := 16);`
171
172			`PORT (`
173			`SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);`
174			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
175			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
176			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
177			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
178			`S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
179			`S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
180			`S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
181			`S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
182			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
183
184			`END mux8to1;`
185
186			`ARCHITECTURE Behavioral OF mux8to1 IS`
187
188			`BEGIN -- Behavioral`
189
190			`WITH SEL SELECT`
191			`Y <=`
192			`S0 WHEN "000",`
193			`S1 WHEN "001",`
194			`S2 WHEN "010",`
195			`S3 WHEN "011",`
196			`S4 WHEN "100",`
197			`S5 WHEN "101",`
198			`S6 WHEN "110",`
199			`S7 WHEN "111",`
200			`S0 WHEN OTHERS;`
201
202			`END Behavioral;`
203
204			`LIBRARY IEEE;`
205			`USE IEEE.std_logic_1164.ALL;`
206			`USE ieee.numeric_std.ALL;`
207
208			`ENTITY mux16to1 IS`
209
210			`GENERIC (`
211			`w_data : NATURAL RANGE 1 TO 32 := 16);`
212
213			`PORT (`
214			`SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);`
215			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
216			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
217			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
218			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
219			`S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
220			`S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
221			`S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
222			`S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
223			`S8 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
224			`S9 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
225			`S10 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
226			`S11 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
227			`S12 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
228			`S13 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
229			`S14 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
230			`S15 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
231			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
232
233			`END mux16to1;`
234
235			`ARCHITECTURE Behavioral OF mux16to1 IS`
236
237			`BEGIN -- Behavioral`
238
239			`WITH SEL SELECT`
240			`Y <=`
241			`S0 WHEN "0000",`
242			`S1 WHEN "0001",`
243			`S2 WHEN "0010",`
244			`S3 WHEN "0011",`
245			`S4 WHEN "0100",`
246			`S5 WHEN "0101",`
247			`S6 WHEN "0110",`
248			`S7 WHEN "0111",`
249			`S8 WHEN "1000",`
250			`S9 WHEN "1001",`
251			`S10 WHEN "1010",`
252			`S11 WHEN "1011",`
253			`S12 WHEN "1100",`
254			`S13 WHEN "1101",`
255			`S14 WHEN "1110",`
256			`S15 WHEN "1111",`
257			`S0 WHEN OTHERS;`
258
259			`END Behavioral;`
260
261			`LIBRARY IEEE;`
262			`USE IEEE.std_logic_1164.ALL;`
263			`USE work.mux_parts.ALL;`
264
265			`ENTITY mux32to1 IS`
266
267			`GENERIC (`
268			`w_data : NATURAL RANGE 1 TO 32 := 16);`
269
270			`PORT (`
271			`SEL : IN STD_LOGIC_VECTOR(4 DOWNTO 0);`
272			`S0 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
273			`S1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
274			`S2 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
275			`S3 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
276			`S4 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
277			`S5 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
278			`S6 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
279			`S7 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
280			`S8 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
281			`S9 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
282			`S10 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
283			`S11 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
284			`S12 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
285			`S13 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
286			`S14 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
287			`S15 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
288			`S16 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
289			`S17 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
290			`S18 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
291			`S19 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
292			`S20 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
293			`S21 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
294			`S22 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
295			`S23 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
296			`S24 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
297			`S25 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
298			`S26 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
299			`S27 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
300			`S28 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
301			`S29 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
302			`S30 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
303			`S31 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
304			`Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));`
305
306			`END mux32to1;`
307
308			`ARCHITECTURE Behavioral OF mux32to1 IS`
309
310			`SIGNAL M1_Y : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
311			`SIGNAL M2_Y : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);`
312
313			`SIGNAL sub_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);`
314			`SIGNAL out_sel : STD_LOGIC_VECTOR(0 DOWNTO 0);`
315
316			`BEGIN -- Behavioral`
317
318			`sub_sel <= SEL(3 DOWNTO 0);`
319			`out_sel <= SEL(4 DOWNTO 4);`
320
321			`M1 : mux16to1`
322			`GENERIC MAP (`
323			`w_data => w_data)`
324			`PORT MAP (`
325			`SEL => sub_sel,`
326			`S0 => S0,`
327			`S1 => S1,`
328			`S2 => S2,`
329			`S3 => S3,`
330			`S4 => S4,`
331			`S5 => S5,`
332			`S6 => S6,`
333			`S7 => S7,`
334			`S8 => S8,`
335			`S9 => S9,`
336			`S10 => S10,`
337			`S11 => S11,`
338			`S12 => S12,`
339			`S13 => S13,`
340			`S14 => S14,`
341			`S15 => S15,`
342			`Y => M1_Y);`
343
344			`M2 : mux16to1`
345			`GENERIC MAP (`
346			`w_data => w_data)`
347			`PORT MAP (`
348			`SEL => sub_sel,`
349			`S0 => S16,`
350			`S1 => S17,`
351			`S2 => S18,`
352			`S3 => S19,`
353			`S4 => S20,`
354			`S5 => S21,`
355			`S6 => S22,`
356			`S7 => S23,`
357			`S8 => S24,`
358			`S9 => S25,`
359			`S10 => S26,`
360			`S11 => S27,`
361			`S12 => S28,`
362			`S13 => S29,`
363			`S14 => S30,`
364			`S15 => S31,`
365			`Y => M2_Y);`
366
367			`M3 : mux2to1`
368			`GENERIC MAP (`
369			`w_data => w_data)`
370			`PORT MAP (`
371			`SEL => out_sel,`
372			`S0 => M1_Y,`
373			`S1 => M2_Y,`
374			`Y => Y);`
375
376			`END Behavioral;`