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[/] [xucpu/] [trunk/] [src/] [io/] [tty_out.vhdl] - Blame information for rev 5

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1 2 lcdsgmtr
-- Copyright 2015, Jürgen Defurne
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--
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-- This file is part of the Experimental Unstable CPU System.
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--
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-- The Experimental Unstable CPU System Is free software: you can redistribute
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-- it and/or modify it under the terms of the GNU Lesser General Public License
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-- as published by the Free Software Foundation, either version 3 of the
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-- License, or (at your option) any later version.
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--
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-- The Experimental Unstable CPU System is distributed in the hope that it will
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-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
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-- General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with Experimental Unstable CPU System. If not, see
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-- http://www.gnu.org/licenses/lgpl.txt.
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE work.system_package.ALL;
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ENTITY tty_out IS
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  PORT (
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    reset    : IN  STD_LOGIC;
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    clock    : IN  STD_LOGIC;
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    rd       : IN  STD_LOGIC;
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    wr       : IN  STD_LOGIC;
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    data_in  : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
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    data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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    address  : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
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    tx       : OUT STD_LOGIC);
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END tty_out;
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ARCHITECTURE Behavioral OF tty_out IS
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  SIGNAL data   : STD_LOGIC_VECTOR(7 DOWNTO 0);
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  SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0);
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BEGIN
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  -- purpose: Base system for serial out state machine
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  -- type   : sequential
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  -- inputs : clock, reset
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  -- outputs: 
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  main : PROCESS (clock, reset)
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  BEGIN  -- PROCESS main
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    IF reset = '0' THEN                 -- asynchronous reset (active low)
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      data   <= X"00";
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      status <= X"00";
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      tx     <= '0';
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    ELSIF rising_edge(clock) THEN       -- rising clock edge
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    END IF;
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  END PROCESS main;
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END Behavioral;
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