Subversion Repositories xucpu

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE work.S2LIB.ALL;

ENTITY S2 IS

  PORT (

    CLOCK  : IN  STD_LOGIC;

    RESET  : IN  STD_LOGIC;

    LED    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

    SWITCH : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);

    BUTTON : IN  STD_LOGIC_VECTOR(4 DOWNTO 0));

END ENTITY S2;

ARCHITECTURE Structural OF S2 IS

  SIGNAL CLK : STD_LOGIC;

  SIGNAL RST : STD_LOGIC;

  SIGNAL DATA_BUS    : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL ADDRESS_BUS : STD_LOGIC_VECTOR(14 DOWNTO 0);

  SIGNAL RD          : STD_LOGIC;

  SIGNAL WR          : STD_LOGIC;

  SIGNAL BA_ADDR_SEL : STD_LOGIC;

  SIGNAL BA_ICC_ACK  : STD_LOGIC;

  SIGNAL BA_DCC_ACK  : STD_LOGIC;

  SIGNAL ICC_RD      : STD_LOGIC;

  SIGNAL ICC_WR      : STD_LOGIC;

  SIGNAL ICC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);

  SIGNAL ICC_DATA    : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL DCC_RD      : STD_LOGIC;

  SIGNAL DCC_WR      : STD_LOGIC;

  SIGNAL DCC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);

  SIGNAL DCC_DATA    : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL CPU_IF          : STD_LOGIC;

  SIGNAL CPU_INSTR_ADDR  : STD_LOGIC_VECTOR(14 DOWNTO 0);

  SIGNAL CPU_INSTRUCTION : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL CPU_RD        : STD_LOGIC;

  SIGNAL CPU_WR        : STD_LOGIC;

  SIGNAL CPU_DATA_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);

  SIGNAL CPU_DATA_OUT  : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL CPU_DATA_IN   : STD_LOGIC_VECTOR(15 DOWNTO 0);

  SIGNAL MEM_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);

BEGIN  -- ARCHITECTURE Structural

  CLK <= CLOCK;

  RST <= RESET;

  BA1 : S2ARB

    PORT MAP (

      -- Main component connections

      CLK               => CLK,

      RST               => RST,

      -- Bus requests from ICC

      I_RD_ICC          => ICC_RD,

      I_WR_ICC          => ICC_WR,

      -- Bus requests from DCC

      I_RD_DCC          => DCC_RD,

      I_WR_DCC          => DCC_WR,

      -- Arbiter control signals

      O_ADDRESS_MUX_SEL => BA_ADDR_SEL,

      O_ACK_ICC         => BA_ICC_ACK,

      O_ACK_DCC         => BA_DCC_ACK);

  ICC1 : S2ICC

    PORT MAP (

      -- Main component connections

      CLK               => CLK,

      RST               => RST,

      -- To main bus

      O_ADDRESS         => ICC_ADDRESS,

      O_DATA            => ICC_DATA,

      O_RD              => ICC_RD,

      O_WR              => ICC_WR,

      -- From bus arbiter

      I_ACK             => BA_ICC_ACK,

      -- From main bus

      I_ADDRESS         => ADDRESS_BUS,

      I_DATA            => DATA_BUS,

      I_RD              => RD,

      I_WR              => WR,

      -- CPU specific connections

      I_CPU_IF          => CPU_IF,

      I_CPU_INSTR_ADDR  => CPU_INSTR_ADDR,

      O_CPU_INSTRUCTION => CPU_INSTRUCTION);

  DCC1 : S2DCC

    PORT MAP (

      -- Main component connections

      CLK             => CLK,

      RST             => RST,

      -- To main bus

      O_ADDRESS       => DCC_ADDRESS,

      O_DATA          => DCC_DATA,

      O_RD            => DCC_RD,

      O_WR            => DCC_WR,

      -- From bus arbiter

      I_ACK           => BA_DCC_ACK,

      -- From main bus

      I_ADDRESS       => ADDRESS_BUS,

      I_DATA          => DATA_BUS,

      I_RD            => RD,

      I_WR            => WR,

      -- CPU specific connections

      I_CPU_RD        => CPU_RD,

      I_CPU_WR        => CPU_WR,

      I_CPU_DATA_ADDR => CPU_DATA_ADDR,

      I_CPU_DATA      => CPU_DATA_OUT,

      O_CPU_DATA      => CPU_DATA_IN);

  CPU1 : S2CPU

    PORT MAP (

      -- Main component connections

      CLK           => CLK,

      RST           => RST,

      -- Instruction cache connections

      O_IF          => CPU_IF,

      O_INSTR_ADDR  => CPU_INSTR_ADDR,

      I_INSTRUCTION => CPU_INSTRUCTION,

      -- Data cache connections

      O_RD          => CPU_RD,

      O_WR          => CPU_WR,

      O_DATA_ADDR   => CPU_DATA_ADDR,

      O_DATA        => CPU_DATA_OUT,

      I_DATA        => CPU_DATA_IN);

  MEM1 : S2MEM

    PORT MAP (

      CLK       => CLK,

      RST       => RST,

      I_RD      => RD,

      I_WR      => WR,

      I_ADDRESS => ADDRESS_BUS,

      I_DATA    => DATA_BUS,

      O_DATA    => MEM_DATA);

END ARCHITECTURE Structural;