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[/] [xucpu/] [trunk/] [src/] [system/] [S2.vhdl] - Blame information for rev 31

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.S2LIB.ALL;
 
ENTITY S2 IS
 
  PORT (
    CLOCK  : IN  STD_LOGIC;
    RESET  : IN  STD_LOGIC;
    LED    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    SWITCH : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    BUTTON : IN  STD_LOGIC_VECTOR(4 DOWNTO 0));
 
END ENTITY S2;
 
ARCHITECTURE Structural OF S2 IS
 
  SIGNAL CLK : STD_LOGIC;
  SIGNAL RST : STD_LOGIC;
 
  SIGNAL DATA_BUS    : STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL ADDRESS_BUS : STD_LOGIC_VECTOR(14 DOWNTO 0);
  SIGNAL RD          : STD_LOGIC;
  SIGNAL WR          : STD_LOGIC;
 
  SIGNAL BA_ADDR_SEL : STD_LOGIC;
  SIGNAL BA_ICC_ACK  : STD_LOGIC;
  SIGNAL BA_DCC_ACK  : STD_LOGIC;
 
  SIGNAL ICC_RD      : STD_LOGIC;
  SIGNAL ICC_WR      : STD_LOGIC;
  SIGNAL ICC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
  SIGNAL ICC_DATA    : STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL DCC_RD      : STD_LOGIC;
  SIGNAL DCC_WR      : STD_LOGIC;
  SIGNAL DCC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
  SIGNAL DCC_DATA    : STD_LOGIC_VECTOR(15 DOWNTO 0);
 
  SIGNAL CPU_IF          : STD_LOGIC;
  SIGNAL CPU_INSTR_ADDR  : STD_LOGIC_VECTOR(14 DOWNTO 0);
  SIGNAL CPU_INSTRUCTION : STD_LOGIC_VECTOR(15 DOWNTO 0);
 
  SIGNAL CPU_RD        : STD_LOGIC;
  SIGNAL CPU_WR        : STD_LOGIC;
  SIGNAL CPU_DATA_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
  SIGNAL CPU_DATA_OUT  : STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL CPU_DATA_IN   : STD_LOGIC_VECTOR(15 DOWNTO 0);
 
  SIGNAL MEM_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
 
BEGIN  -- ARCHITECTURE Structural
 
  BA1 : S2ARB
    PORT MAP (
      -- Main component connections
      CLK               => CLK,
      RST               => RST,
      -- Bus requests from ICC
      I_RD_ICC          => ICC_RD,
      I_WR_ICC          => ICC_WR,
      -- Bus requests from DCC
      I_RD_DCC          => DCC_RD,
      I_WR_DCC          => DCC_WR,
      -- Arbiter control signals
      O_ADDRESS_MUX_SEL => BA_ADDR_SEL,
      O_ACK_ICC         => BA_ICC_ACK,
      O_ACK_DCC         => BA_DCC_ACK);
 
 
  ICC1 : S2ICC
    PORT MAP (
      -- Main component connections
      CLK               => CLK,
      RST               => RST,
      -- To main bus
      O_ADDRESS         => ICC_ADDRESS,
      O_DATA            => ICC_DATA,
      O_RD              => ICC_RD,
      O_WR              => ICC_WR,
      -- From bus arbiter
      I_ACK             => BA_ICC_ACK,
      -- From main bus
      I_ADDRESS         => ADDRESS_BUS,
      I_DATA            => DATA_BUS,
      I_RD              => RD,
      I_WR              => WR,
      -- CPU specific connections
      I_CPU_IF          => CPU_IF,
      I_CPU_INSTR_ADDR  => CPU_INSTR_ADDR,
      I_CPU_INSTRUCTION => CPU_INSTRUCTION);
 
  DCC1 : S2DCC
    PORT MAP (
      -- Main component connections
      CLK             => CLK,
      RST             => RST,
      -- To main bus
      O_ADDRESS       => DCC_ADDRESS,
      O_DATA          => DCC_DATA,
      O_RD            => DCC_RD,
      O_WR            => DCC_WR,
      -- From bus arbiter
      I_ACK           => BA_DCC_ACK,
      -- From main bus
      I_ADDRESS       => ADDRESS_BUS,
      I_DATA          => DATA_BUS,
      I_RD            => RD,
      I_WR            => WR,
      -- CPU specific connections
      I_CPU_RD        => CPU_RD,
      I_CPU_WR        => CPU_WR,
      I_CPU_DATA_ADDR => CPU_DATA_ADDRESS,
      I_CPU_DATA      => CPU_DATA_OUT,
      O_CPU_DATA      => CPU_DATA_IN);
 
  CPU1 : S2CPU
    PORT MAP (
      -- Main component connections
      CLK           => CLK,
      RST           => RST,
      -- Instruction cache connections
      O_IF          => CPU_IF,
      O_INSTR_ADDR  => CPU_INSTR_ADDR,
      I_INSTRUCTION => CPU_INSTRUCTION,
      -- Data cache connections
      O_RD          => CPU_RD,
      O_WR          => CPU_WR,
      O_DATA_ADDR   => CPU_DATA_ADDRESS,
      O_DATA        => CPU_DATA_OUT,
      I_DATA        => CPU_DATA_IN);
 
  MEM1 : S2MEM
    PORT MAP (
      CLK       => CLK,
      RST       => RST,
      I_RD      => RD,
      I_WR      => WR,
      I_ADDRESS => ADDRESS_BUS,
      I_DATA    => DATA_BUS,
      O_DATA    => MEM_DATA);
 
 
 
 
 
END ARCHITECTURE Structural;

Line No.	Rev	Author	Line
1	31	lcdsgmtr	`LIBRARY ieee;`
2			`USE ieee.std_logic_1164.ALL;`
3			`USE ieee.numeric_std.ALL;`
4			`USE work.S2LIB.ALL;`
5
6			`ENTITY S2 IS`
7
8			`PORT (`
9			`CLOCK : IN STD_LOGIC;`
10			`RESET : IN STD_LOGIC;`
11			`LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
12			`SWITCH : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
13			`BUTTON : IN STD_LOGIC_VECTOR(4 DOWNTO 0));`
14
15			`END ENTITY S2;`
16
17			`ARCHITECTURE Structural OF S2 IS`
18
19			`SIGNAL CLK : STD_LOGIC;`
20			`SIGNAL RST : STD_LOGIC;`
21
22			`SIGNAL DATA_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0);`
23			`SIGNAL ADDRESS_BUS : STD_LOGIC_VECTOR(14 DOWNTO 0);`
24			`SIGNAL RD : STD_LOGIC;`
25			`SIGNAL WR : STD_LOGIC;`
26
27			`SIGNAL BA_ADDR_SEL : STD_LOGIC;`
28			`SIGNAL BA_ICC_ACK : STD_LOGIC;`
29			`SIGNAL BA_DCC_ACK : STD_LOGIC;`
30
31			`SIGNAL ICC_RD : STD_LOGIC;`
32			`SIGNAL ICC_WR : STD_LOGIC;`
33			`SIGNAL ICC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);`
34			`SIGNAL ICC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);`
35			`SIGNAL DCC_RD : STD_LOGIC;`
36			`SIGNAL DCC_WR : STD_LOGIC;`
37			`SIGNAL DCC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);`
38			`SIGNAL DCC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);`
39
40			`SIGNAL CPU_IF : STD_LOGIC;`
41			`SIGNAL CPU_INSTR_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);`
42			`SIGNAL CPU_INSTRUCTION : STD_LOGIC_VECTOR(15 DOWNTO 0);`
43
44			`SIGNAL CPU_RD : STD_LOGIC;`
45			`SIGNAL CPU_WR : STD_LOGIC;`
46			`SIGNAL CPU_DATA_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);`
47			`SIGNAL CPU_DATA_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);`
48			`SIGNAL CPU_DATA_IN : STD_LOGIC_VECTOR(15 DOWNTO 0);`
49
50			`SIGNAL MEM_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);`
51
52			`BEGIN -- ARCHITECTURE Structural`
53
54			`BA1 : S2ARB`
55			`PORT MAP (`
56			`-- Main component connections`
57			`CLK => CLK,`
58			`RST => RST,`
59			`-- Bus requests from ICC`
60			`I_RD_ICC => ICC_RD,`
61			`I_WR_ICC => ICC_WR,`
62			`-- Bus requests from DCC`
63			`I_RD_DCC => DCC_RD,`
64			`I_WR_DCC => DCC_WR,`
65			`-- Arbiter control signals`
66			`O_ADDRESS_MUX_SEL => BA_ADDR_SEL,`
67			`O_ACK_ICC => BA_ICC_ACK,`
68			`O_ACK_DCC => BA_DCC_ACK);`
69
70
71			`ICC1 : S2ICC`
72			`PORT MAP (`
73			`-- Main component connections`
74			`CLK => CLK,`
75			`RST => RST,`
76			`-- To main bus`
77			`O_ADDRESS => ICC_ADDRESS,`
78			`O_DATA => ICC_DATA,`
79			`O_RD => ICC_RD,`
80			`O_WR => ICC_WR,`
81			`-- From bus arbiter`
82			`I_ACK => BA_ICC_ACK,`
83			`-- From main bus`
84			`I_ADDRESS => ADDRESS_BUS,`
85			`I_DATA => DATA_BUS,`
86			`I_RD => RD,`
87			`I_WR => WR,`
88			`-- CPU specific connections`
89			`I_CPU_IF => CPU_IF,`
90			`I_CPU_INSTR_ADDR => CPU_INSTR_ADDR,`
91			`I_CPU_INSTRUCTION => CPU_INSTRUCTION);`
92
93			`DCC1 : S2DCC`
94			`PORT MAP (`
95			`-- Main component connections`
96			`CLK => CLK,`
97			`RST => RST,`
98			`-- To main bus`
99			`O_ADDRESS => DCC_ADDRESS,`
100			`O_DATA => DCC_DATA,`
101			`O_RD => DCC_RD,`
102			`O_WR => DCC_WR,`
103			`-- From bus arbiter`
104			`I_ACK => BA_DCC_ACK,`
105			`-- From main bus`
106			`I_ADDRESS => ADDRESS_BUS,`
107			`I_DATA => DATA_BUS,`
108			`I_RD => RD,`
109			`I_WR => WR,`
110			`-- CPU specific connections`
111			`I_CPU_RD => CPU_RD,`
112			`I_CPU_WR => CPU_WR,`
113			`I_CPU_DATA_ADDR => CPU_DATA_ADDRESS,`
114			`I_CPU_DATA => CPU_DATA_OUT,`
115			`O_CPU_DATA => CPU_DATA_IN);`
116
117			`CPU1 : S2CPU`
118			`PORT MAP (`
119			`-- Main component connections`
120			`CLK => CLK,`
121			`RST => RST,`
122			`-- Instruction cache connections`
123			`O_IF => CPU_IF,`
124			`O_INSTR_ADDR => CPU_INSTR_ADDR,`
125			`I_INSTRUCTION => CPU_INSTRUCTION,`
126			`-- Data cache connections`
127			`O_RD => CPU_RD,`
128			`O_WR => CPU_WR,`
129			`O_DATA_ADDR => CPU_DATA_ADDRESS,`
130			`O_DATA => CPU_DATA_OUT,`
131			`I_DATA => CPU_DATA_IN);`
132
133			`MEM1 : S2MEM`
134			`PORT MAP (`
135			`CLK => CLK,`
136			`RST => RST,`
137			`I_RD => RD,`
138			`I_WR => WR,`
139			`I_ADDRESS => ADDRESS_BUS,`
140			`I_DATA => DATA_BUS,`
141			`O_DATA => MEM_DATA);`
142
143
144
145
146
147			`END ARCHITECTURE Structural;`

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[/] [xucpu/] [trunk/] [src/] [system/] [S2.vhdl] - Blame information for rev 31