OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [system/] [S2LIB.vhdl] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 33 lcdsgmtr 
LIBRARY ieee;
2 
USE ieee.std_logic_1164.ALL;
3 
 
4 31 lcdsgmtr 
PACKAGE S2LIB IS
5 
 
6 
  COMPONENT S2ARB IS
7 
    PORT (
8 
      I_RD_ICC          : IN  STD_LOGIC;
9 
      I_WR_ICC          : IN  STD_LOGIC;
10 
      I_RD_DCC          : IN  STD_LOGIC;
11 
      I_WR_DCC          : IN  STD_LOGIC;
12 
      O_ADDRESS_MUX_SEL : OUT STD_LOGIC;
13 
      O_ACK_ICC         : OUT STD_LOGIC;
14 
      O_ACK_DCC         : OUT STD_LOGIC;
15 
      CLK               : IN  STD_LOGIC;
16 
      RST               : IN  STD_LOGIC);
17 
  END COMPONENT S2ARB;
18 
 
19 
  COMPONENT S2ICC IS
20 
    PORT (
21 
      CLK               : IN  STD_LOGIC;
22 
      RST               : IN  STD_LOGIC;
23 
      O_ADDRESS         : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
24 
      O_DATA            : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
25 
      O_RD              : OUT STD_LOGIC;
26 
      O_WR              : OUT STD_LOGIC;
27 
      I_ACK             : IN  STD_LOGIC;
28 
      I_ADDRESS         : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
29 
      I_DATA            : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
30 
      I_RD              : IN  STD_LOGIC;
31 
      I_WR              : IN  STD_LOGIC;
32 
      I_CPU_IF          : IN  STD_LOGIC;
33 
      I_CPU_INSTR_ADDR  : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
34 
      O_CPU_INSTRUCTION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
35 
  END COMPONENT S2ICC;
36 
 
37 
  COMPONENT S2DCC IS
38 
    PORT (
39 
      CLK             : IN  STD_LOGIC;
40 
      RST             : IN  STD_LOGIC;
41 
      O_ADDRESS       : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
42 
      O_DATA          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
43 
      O_RD            : OUT STD_LOGIC;
44 
      O_WR            : OUT STD_LOGIC;
45 
      I_ACK           : IN  STD_LOGIC;
46 
      I_ADDRESS       : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
47 
      I_DATA          : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
48 
      I_RD              : IN  STD_LOGIC;
49 
      I_WR              : IN  STD_LOGIC;
50 
      I_CPU_RD        : IN  STD_LOGIC;
51 
      I_CPU_WR        : IN  STD_LOGIC;
52 
      I_CPU_DATA_ADDR : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
53 
      I_CPU_DATA      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
54 
      O_CPU_DATA      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
55 
  END COMPONENT S2DCC;
56 
 
57 
  COMPONENT S2CPU IS
58 
    PORT (
59 
      CLK           : IN  STD_LOGIC;
60 
      RST           : IN  STD_LOGIC;
61 
      O_IF          : OUT STD_LOGIC;
62 
      O_INSTR_ADDR  : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
63 
      I_INSTRUCTION : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
64 
      O_RD          : OUT STD_LOGIC;
65 
      O_WR          : OUT STD_LOGIC;
66 
      O_DATA_ADDR   : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
67 
      O_DATA        : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
68 
      I_DATA        : IN  STD_LOGIC_VECTOR(15 DOWNTO 0));
69 
  END COMPONENT S2CPU;
70 
 
71 
  COMPONENT S2MEM IS
72 
    PORT (
73 
      CLK       : IN  STD_LOGIC;
74 
      RST       : IN  STD_LOGIC;
75 
      I_RD      : IN  STD_LOGIC;
76 
      I_WR      : IN  STD_LOGIC;
77 
      I_ADDRESS : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
78 
      I_DATA    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
79 
      O_DATA    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
80 
  END COMPONENT S2MEM;
81 
 
82 
END PACKAGE S2LIB;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.