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[/] [xucpu/] [trunk/] [src/] [system/] [S2LIB.vhdl] - Blame information for rev 31

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Line No. Rev Author Line
1 31 lcdsgmtr 
PACKAGE S2LIB IS
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  COMPONENT S2ARB IS
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    PORT (
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      I_RD_ICC          : IN  STD_LOGIC;
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      I_WR_ICC          : IN  STD_LOGIC;
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      I_RD_DCC          : IN  STD_LOGIC;
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      I_WR_DCC          : IN  STD_LOGIC;
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      O_ADDRESS_MUX_SEL : OUT STD_LOGIC;
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      O_ACK_ICC         : OUT STD_LOGIC;
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      O_ACK_DCC         : OUT STD_LOGIC;
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      CLK               : IN  STD_LOGIC;
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      RST               : IN  STD_LOGIC);
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  END COMPONENT S2ARB;
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  COMPONENT S2ICC IS
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    PORT (
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      CLK               : IN  STD_LOGIC;
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      RST               : IN  STD_LOGIC;
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      O_ADDRESS         : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
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      O_DATA            : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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      O_RD              : OUT STD_LOGIC;
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      O_WR              : OUT STD_LOGIC;
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      I_ACK             : IN  STD_LOGIC;
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      I_ADDRESS         : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
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      I_DATA            : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
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      I_RD              : IN  STD_LOGIC;
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      I_WR              : IN  STD_LOGIC;
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      I_CPU_IF          : IN  STD_LOGIC;
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      I_CPU_INSTR_ADDR  : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
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      O_CPU_INSTRUCTION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
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  END COMPONENT S2ICC;
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  COMPONENT S2DCC IS
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    PORT (
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      CLK             : IN  STD_LOGIC;
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      RST             : IN  STD_LOGIC;
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      O_ADDRESS       : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
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      O_DATA          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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      O_RD            : OUT STD_LOGIC;
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      O_WR            : OUT STD_LOGIC;
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      I_ACK           : IN  STD_LOGIC;
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      I_ADDRESS       : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
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      I_DATA          : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
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      I_RD              : IN  STD_LOGIC;
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      I_WR              : IN  STD_LOGIC;
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      I_CPU_RD        : IN  STD_LOGIC;
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      I_CPU_WR        : IN  STD_LOGIC;
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      I_CPU_DATA_ADDR : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
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      I_CPU_DATA      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
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      O_CPU_DATA      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
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  END COMPONENT S2DCC;
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  COMPONENT S2CPU IS
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    PORT (
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      CLK           : IN  STD_LOGIC;
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      RST           : IN  STD_LOGIC;
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      O_IF          : OUT STD_LOGIC;
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      O_INSTR_ADDR  : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
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      I_INSTRUCTION : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
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      O_RD          : OUT STD_LOGIC;
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      O_WR          : OUT STD_LOGIC;
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      O_DATA_ADDR   : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
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      O_DATA        : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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      I_DATA        : IN  STD_LOGIC_VECTOR(15 DOWNTO 0));
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  END COMPONENT S2CPU;
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  COMPONENT S2MEM IS
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    PORT (
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      CLK       : IN  STD_LOGIC;
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      RST       : IN  STD_LOGIC;
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      I_RD      : IN  STD_LOGIC;
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      I_WR      : IN  STD_LOGIC;
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      I_ADDRESS : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
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      I_DATA    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
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      O_DATA    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
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  END COMPONENT S2MEM;
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END PACKAGE S2LIB;

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