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-- Copyright 2015, J�rgen Defurne
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
ARCHITECTURE Mealy OF uctrl IS
 
  TYPE uCtrl_state IS (
    S_RST,
    S_DECODE,
    S_FETCH,
    S_UOP_P1,
    S_UOP_P2,
    S_BOP_P1,
    S_BOP_P2,
    S_LD_RV,
    S_LD_RV_2,
    S_LD_RR,
    S_LD_RR_2,
    S_LD_RM,
    S_LD_RM_2,
    S_LD_MR,
    S_LD_MR_2,
    S_GO_ADR,
    S_GO_ADR_2,
    S_GO_REG,
    S_GO_REG_2,
    S_JZ_P0,
    S_JZ_P1,
    S_JZ_P2,
    S_JNZ_P0,
    S_JNZ_P1,
    S_JNZ_P2,
    S_HALT,
    S_RETI,
    S_RETI_2,
    S_ILL
    );
 
  SIGNAL NEXT_STATE : uCtrl_state;
  SIGNAL CURR_STATE : uCtrl_state;
 
  SIGNAL LD_INSTR : STD_LOGIC;
  SIGNAL DECODING : STD_LOGIC;
 
  SIGNAL OPERATION  : STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL REG_ADDR_A : STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL REG_ADDR_B : STD_LOGIC_VECTOR(3 DOWNTO 0);
 
BEGIN  -- ARCHITECTURE Mealy
 
-- purpose: Next state functionality
-- type   : combinational
-- inputs : IR_IN,ZERO,INT,RST,CURR_STATE
-- outputs: 
  NEXT_ST1 : PROCESS (CURR_STATE, IR_IN, INT, RST, ZERO)
    VARIABLE I_ADDR : uCtrl_state;
  BEGIN  -- PROCESS uCTRL
 
    IF RST = '1' THEN
      NEXT_STATE <= S_RST;
    ELSE
 
      CASE IR_IN(15 DOWNTO 12) IS
        WHEN "0000" => I_ADDR := S_HALT;
        WHEN "0001" => I_ADDR := S_GO_ADR;
        WHEN "0010" => I_ADDR := S_GO_REG;
        WHEN "0011" => I_ADDR := S_LD_RV;
        WHEN "0100" => I_ADDR := S_LD_RR;
        WHEN "0101" => I_ADDR := S_LD_RM;
        WHEN "0110" => I_ADDR := S_LD_MR;
        WHEN "0111" => I_ADDR := S_BOP_P1;
        WHEN "1000" => I_ADDR := S_UOP_P1;
        WHEN "1001" => I_ADDR := S_JZ_P0;
        WHEN "1010" => I_ADDR := S_JNZ_P0;
        WHEN "1011" => I_ADDR := S_RETI;
        WHEN "1100" => I_ADDR := S_ILL;
        WHEN "1101" => I_ADDR := S_ILL;
        WHEN "1110" => I_ADDR := S_ILL;
        WHEN "1111" => I_ADDR := S_ILL;
        WHEN OTHERS => I_ADDR := S_ILL;
      END CASE;
 
      CASE CURR_STATE IS
        WHEN S_RST =>
          NEXT_STATE <= S_FETCH;
        WHEN S_FETCH =>
          NEXT_STATE <= S_DECODE;
        WHEN S_DECODE =>
          NEXT_STATE <= I_ADDR;
        WHEN S_UOP_P1 =>
          NEXT_STATE <= S_UOP_P2;
        WHEN S_UOP_P2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_BOP_P1 =>
          NEXT_STATE <= S_BOP_P2;
        WHEN S_BOP_P2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_LD_RV =>
          NEXT_STATE <= S_LD_RV_2;
        WHEN S_LD_RV_2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_LD_RR =>
          NEXT_STATE <= S_LD_RR_2;
        WHEN S_LD_RR_2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_LD_RM =>
          NEXT_STATE <= S_LD_RM_2;
        WHEN S_LD_RM_2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_LD_MR =>
          NEXT_STATE <= S_LD_MR_2;
        WHEN S_LD_MR_2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_GO_ADR =>
          NEXT_STATE <= S_GO_ADR_2;
        WHEN S_GO_ADR_2 =>
          NEXT_STATE <= I_ADDR;
        WHEN S_GO_REG =>
          NEXT_STATE <= S_GO_REG_2;
 
        WHEN S_JZ_P0 =>
          NEXT_STATE <= S_JZ_P1;
        WHEN S_JZ_P1 =>
          IF ZERO = '1' THEN
            NEXT_STATE <= S_FETCH;
          ELSE
            NEXT_STATE <= S_JZ_P2;
          END IF;
        WHEN S_JZ_P2 =>
          NEXT_STATE <= I_ADDR;
 
        WHEN S_JNZ_P0 =>
          NEXT_STATE <= S_JNZ_P1;
        WHEN S_JNZ_P1 =>
          IF ZERO = '1' THEN
            NEXT_STATE <= S_FETCH;
          ELSE
            NEXT_STATE <= S_JNZ_P2;
          END IF;
        WHEN S_JNZ_P2 =>
          NEXT_STATE <= I_ADDR;
 
        WHEN S_HALT =>
          NEXT_STATE <= S_HALT;
        WHEN S_RETI =>
          NEXT_STATE <= S_RETI_2;
        WHEN S_RETI_2 =>
          NEXT_STATE <= S_DECODE;
        WHEN S_ILL =>
          NEXT_STATE <= S_ILL;
        WHEN OTHERS =>
          NEXT_STATE <= S_DECODE;
      END CASE;
    END IF;
  END PROCESS NEXT_ST1;
 
  -- State register logic
  STATE_REG1 : PROCESS (CLK, RST)
  BEGIN
    IF rising_edge(CLK) THEN
      IF RST = '1' THEN
        CURR_STATE <= S_RST;
      ELSE
        CURR_STATE <= NEXT_STATE;
      END IF;
    END IF;
  END PROCESS STATE_REG1;
 
  -- Instruction values
  INSTR_REG1 : PROCESS (CLK, RST)
  BEGIN
    IF rising_edge(CLK) THEN
      IF RST = '1' THEN
        OPERATION  <= "0000";
        REG_ADDR_A <= "0000";
        REG_ADDR_B <= "0000";
      ELSE
        IF LD_INSTR = '1' THEN
          OPERATION  <= IR_IN(11 DOWNTO 8);
          REG_ADDR_A <= IR_IN(7 DOWNTO 4);
          REG_ADDR_B <= IR_IN(3 DOWNTO 0);
        END IF;
      END IF;
    END IF;
  END PROCESS;
 
  ALU_OP <= OPERATION;
  RFA_A  <= REG_ADDR_A;
  RFA_B  <= REG_ADDR_B;
 
  -- Mealy output function logic
  OUT1 : PROCESS (CURR_STATE, RST, INT, IR_IN, DECODING, ZERO)
  BEGIN
 
    -- Make sure that all control signals are initialised
    PC_SRC   <= "011";                  -- Default to PC output
    LD_PC    <= '0';
    LD_IR    <= '0';
    LD_DP    <= '0';
    REG_SRC  <= "101";
    REG_WR   <= '0';
    LD_REG_A <= '0';
    LD_REG_B <= '0';
    LD_MAR   <= '0';
    LD_MDR   <= '0';
    MEM_WR   <= '0';
    LD_INSTR <= '0';
    DECODING <= '0';
 
    CASE CURR_STATE IS
      WHEN S_RST =>
        IF RST = '0' THEN
          PC_SRC <= "100";
          LD_PC  <= '1';
          LD_IR  <= '0';
        END IF;
 
      WHEN S_FETCH =>
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '0';
 
      WHEN S_DECODE =>
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_UOP_P1 =>
        LD_REG_A <= '1';
 
      WHEN S_UOP_P2 =>
        REG_SRC <= "000";
        REG_WR  <= '1';
 
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_BOP_P1 =>
        LD_REG_A <= '1';
        LD_REG_B <= '1';
 
      WHEN S_BOP_P2 =>
        REG_SRC <= "000";
        REG_WR  <= '1';
 
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_LD_RR =>
        LD_REG_B <= '1';
 
      WHEN S_LD_RR_2 =>
        REG_SRC <= "000";
        REG_WR  <= '1';
 
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_LD_RV =>
        PC_SRC <= "001";
        LD_PC  <= '1';
        LD_IR  <= '1';
        LD_DP  <= '0';
 
      WHEN S_LD_RV_2 =>
        REG_SRC <= "010";
        REG_WR  <= '1';
 
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      -- Write data from reg A to address reg B
      WHEN S_LD_MR =>
        LD_MAR <= '1';
        LD_MDR <= '1';
 
      WHEN S_LD_MR_2 =>
        MEM_WR <= '1';
 
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_LD_RM =>
        LD_MAR <= '1';
 
      WHEN S_LD_RM_2 =>
        REG_SRC <= "001";
        REG_WR  <= '1';
 
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_JZ_P0 =>
      WHEN S_JNZ_P0 =>
        NULL;
 
      WHEN S_JZ_P1 =>
        IF ZERO = '1' THEN
          PC_SRC <= "010";
        ELSE
          PC_SRC <= "001";
        END IF;
 
        LD_PC <= '1';
        LD_IR <= '1';
        LD_DP <= '0';
 
      WHEN S_JZ_P2 =>
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
 
      WHEN S_JNZ_P1 =>
        IF ZERO = '0' THEN
          PC_SRC <= "010";
        ELSE
          PC_SRC <= "001";
        END IF;
 
        LD_PC <= '1';
        LD_IR <= '1';
        LD_DP <= '0';
 
      WHEN S_JNZ_P2 =>
        PC_SRC   <= "001";
        LD_PC    <= '1';
        LD_IR    <= '1';
        LD_DP    <= '1';
        LD_INSTR <= '1';
        DECODING <= '1';
      WHEN S_HALT =>
        NULL;
 
      WHEN OTHERS =>
        PC_SRC <= "001";
        LD_PC  <= '1';
        LD_IR  <= '1';
        LD_DP  <= '1';
 
    END CASE;
 
    CASE IR_IN(15 DOWNTO 12) IS
      WHEN "0001" =>
        IF DECODING = '1' THEN
          PC_SRC <= "111";
          LD_PC  <= '1';
        END IF;
 
      WHEN "0011" =>
      WHEN "1001" =>
      WHEN "1010" =>
        IF DECODING = '1' THEN
          LD_IR <= '0';
        END IF;
 
      WHEN OTHERS =>
        NULL;
    END CASE;
 
  END PROCESS OUT1;
 
END ARCHITECTURE Mealy;

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[/] [xucpu/] [trunk/] [src/] [system/] [uctrl.vhdl] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	lcdsgmtr	`-- Copyright 2015, J�rgen Defurne`
2			`--`
3			`-- This file is part of the Experimental Unstable CPU System.`
4			`--`
5			`-- The Experimental Unstable CPU System Is free software: you can redistribute`
6			`-- it and/or modify it under the terms of the GNU Lesser General Public License`
7			`-- as published by the Free Software Foundation, either version 3 of the`
8			`-- License, or (at your option) any later version.`
9			`--`
10			`-- The Experimental Unstable CPU System is distributed in the hope that it will`
11			`-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser`
13			`-- General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU Lesser General Public License`
16			`-- along with Experimental Unstable CPU System. If not, see`
17			`-- http://www.gnu.org/licenses/lgpl.txt.`
18
19
20			`ARCHITECTURE Mealy OF uctrl IS`
21
22			`TYPE uCtrl_state IS (`
23			`S_RST,`
24			`S_DECODE,`
25			`S_FETCH,`
26			`S_UOP_P1,`
27			`S_UOP_P2,`
28			`S_BOP_P1,`
29			`S_BOP_P2,`
30			`S_LD_RV,`
31			`S_LD_RV_2,`
32			`S_LD_RR,`
33			`S_LD_RR_2,`
34			`S_LD_RM,`
35			`S_LD_RM_2,`
36			`S_LD_MR,`
37			`S_LD_MR_2,`
38			`S_GO_ADR,`
39			`S_GO_ADR_2,`
40			`S_GO_REG,`
41			`S_GO_REG_2,`
42			`S_JZ_P0,`
43			`S_JZ_P1,`
44			`S_JZ_P2,`
45			`S_JNZ_P0,`
46			`S_JNZ_P1,`
47			`S_JNZ_P2,`
48			`S_HALT,`
49			`S_RETI,`
50			`S_RETI_2,`
51			`S_ILL`
52			`);`
53
54			`SIGNAL NEXT_STATE : uCtrl_state;`
55			`SIGNAL CURR_STATE : uCtrl_state;`
56
57			`SIGNAL LD_INSTR : STD_LOGIC;`
58			`SIGNAL DECODING : STD_LOGIC;`
59
60			`SIGNAL OPERATION : STD_LOGIC_VECTOR(3 DOWNTO 0);`
61			`SIGNAL REG_ADDR_A : STD_LOGIC_VECTOR(3 DOWNTO 0);`
62			`SIGNAL REG_ADDR_B : STD_LOGIC_VECTOR(3 DOWNTO 0);`
63
64			`BEGIN -- ARCHITECTURE Mealy`
65
66			`-- purpose: Next state functionality`
67			`-- type : combinational`
68			`-- inputs : IR_IN,ZERO,INT,RST,CURR_STATE`
69			`-- outputs:`
70			`NEXT_ST1 : PROCESS (CURR_STATE, IR_IN, INT, RST, ZERO)`
71			`VARIABLE I_ADDR : uCtrl_state;`
72			`BEGIN -- PROCESS uCTRL`
73
74			`IF RST = '1' THEN`
75			`NEXT_STATE <= S_RST;`
76			`ELSE`
77
78			`CASE IR_IN(15 DOWNTO 12) IS`
79			`WHEN "0000" => I_ADDR := S_HALT;`
80			`WHEN "0001" => I_ADDR := S_GO_ADR;`
81			`WHEN "0010" => I_ADDR := S_GO_REG;`
82			`WHEN "0011" => I_ADDR := S_LD_RV;`
83			`WHEN "0100" => I_ADDR := S_LD_RR;`
84			`WHEN "0101" => I_ADDR := S_LD_RM;`
85			`WHEN "0110" => I_ADDR := S_LD_MR;`
86			`WHEN "0111" => I_ADDR := S_BOP_P1;`
87			`WHEN "1000" => I_ADDR := S_UOP_P1;`
88			`WHEN "1001" => I_ADDR := S_JZ_P0;`
89			`WHEN "1010" => I_ADDR := S_JNZ_P0;`
90			`WHEN "1011" => I_ADDR := S_RETI;`
91			`WHEN "1100" => I_ADDR := S_ILL;`
92			`WHEN "1101" => I_ADDR := S_ILL;`
93			`WHEN "1110" => I_ADDR := S_ILL;`
94			`WHEN "1111" => I_ADDR := S_ILL;`
95			`WHEN OTHERS => I_ADDR := S_ILL;`
96			`END CASE;`
97
98			`CASE CURR_STATE IS`
99			`WHEN S_RST =>`
100			`NEXT_STATE <= S_FETCH;`
101			`WHEN S_FETCH =>`
102			`NEXT_STATE <= S_DECODE;`
103			`WHEN S_DECODE =>`
104			`NEXT_STATE <= I_ADDR;`
105			`WHEN S_UOP_P1 =>`
106			`NEXT_STATE <= S_UOP_P2;`
107			`WHEN S_UOP_P2 =>`
108			`NEXT_STATE <= I_ADDR;`
109			`WHEN S_BOP_P1 =>`
110			`NEXT_STATE <= S_BOP_P2;`
111			`WHEN S_BOP_P2 =>`
112			`NEXT_STATE <= I_ADDR;`
113			`WHEN S_LD_RV =>`
114			`NEXT_STATE <= S_LD_RV_2;`
115			`WHEN S_LD_RV_2 =>`
116			`NEXT_STATE <= I_ADDR;`
117			`WHEN S_LD_RR =>`
118			`NEXT_STATE <= S_LD_RR_2;`
119			`WHEN S_LD_RR_2 =>`
120			`NEXT_STATE <= I_ADDR;`
121			`WHEN S_LD_RM =>`
122			`NEXT_STATE <= S_LD_RM_2;`
123			`WHEN S_LD_RM_2 =>`
124			`NEXT_STATE <= I_ADDR;`
125			`WHEN S_LD_MR =>`
126			`NEXT_STATE <= S_LD_MR_2;`
127			`WHEN S_LD_MR_2 =>`
128			`NEXT_STATE <= I_ADDR;`
129			`WHEN S_GO_ADR =>`
130			`NEXT_STATE <= S_GO_ADR_2;`
131			`WHEN S_GO_ADR_2 =>`
132			`NEXT_STATE <= I_ADDR;`
133			`WHEN S_GO_REG =>`
134			`NEXT_STATE <= S_GO_REG_2;`
135
136			`WHEN S_JZ_P0 =>`
137			`NEXT_STATE <= S_JZ_P1;`
138			`WHEN S_JZ_P1 =>`
139			`IF ZERO = '1' THEN`
140			`NEXT_STATE <= S_FETCH;`
141			`ELSE`
142			`NEXT_STATE <= S_JZ_P2;`
143			`END IF;`
144			`WHEN S_JZ_P2 =>`
145			`NEXT_STATE <= I_ADDR;`
146
147			`WHEN S_JNZ_P0 =>`
148			`NEXT_STATE <= S_JNZ_P1;`
149			`WHEN S_JNZ_P1 =>`
150			`IF ZERO = '1' THEN`
151			`NEXT_STATE <= S_FETCH;`
152			`ELSE`
153			`NEXT_STATE <= S_JNZ_P2;`
154			`END IF;`
155			`WHEN S_JNZ_P2 =>`
156			`NEXT_STATE <= I_ADDR;`
157
158			`WHEN S_HALT =>`
159			`NEXT_STATE <= S_HALT;`
160			`WHEN S_RETI =>`
161			`NEXT_STATE <= S_RETI_2;`
162			`WHEN S_RETI_2 =>`
163			`NEXT_STATE <= S_DECODE;`
164			`WHEN S_ILL =>`
165			`NEXT_STATE <= S_ILL;`
166			`WHEN OTHERS =>`
167			`NEXT_STATE <= S_DECODE;`
168			`END CASE;`
169			`END IF;`
170			`END PROCESS NEXT_ST1;`
171
172			`-- State register logic`
173			`STATE_REG1 : PROCESS (CLK, RST)`
174			`BEGIN`
175			`IF rising_edge(CLK) THEN`
176			`IF RST = '1' THEN`
177			`CURR_STATE <= S_RST;`
178			`ELSE`
179			`CURR_STATE <= NEXT_STATE;`
180			`END IF;`
181			`END IF;`
182			`END PROCESS STATE_REG1;`
183
184			`-- Instruction values`
185			`INSTR_REG1 : PROCESS (CLK, RST)`
186			`BEGIN`
187			`IF rising_edge(CLK) THEN`
188			`IF RST = '1' THEN`
189			`OPERATION <= "0000";`
190			`REG_ADDR_A <= "0000";`
191			`REG_ADDR_B <= "0000";`
192			`ELSE`
193			`IF LD_INSTR = '1' THEN`
194			`OPERATION <= IR_IN(11 DOWNTO 8);`
195			`REG_ADDR_A <= IR_IN(7 DOWNTO 4);`
196			`REG_ADDR_B <= IR_IN(3 DOWNTO 0);`
197			`END IF;`
198			`END IF;`
199			`END IF;`
200			`END PROCESS;`
201
202			`ALU_OP <= OPERATION;`
203			`RFA_A <= REG_ADDR_A;`
204			`RFA_B <= REG_ADDR_B;`
205
206			`-- Mealy output function logic`
207			`OUT1 : PROCESS (CURR_STATE, RST, INT, IR_IN, DECODING, ZERO)`
208			`BEGIN`
209
210			`-- Make sure that all control signals are initialised`
211			`PC_SRC <= "011"; -- Default to PC output`
212			`LD_PC <= '0';`
213			`LD_IR <= '0';`
214			`LD_DP <= '0';`
215			`REG_SRC <= "101";`
216			`REG_WR <= '0';`
217			`LD_REG_A <= '0';`
218			`LD_REG_B <= '0';`
219			`LD_MAR <= '0';`
220			`LD_MDR <= '0';`
221			`MEM_WR <= '0';`
222			`LD_INSTR <= '0';`
223			`DECODING <= '0';`
224
225			`CASE CURR_STATE IS`
226			`WHEN S_RST =>`
227			`IF RST = '0' THEN`
228			`PC_SRC <= "100";`
229			`LD_PC <= '1';`
230			`LD_IR <= '0';`
231			`END IF;`
232
233			`WHEN S_FETCH =>`
234			`PC_SRC <= "001";`
235			`LD_PC <= '1';`
236			`LD_IR <= '1';`
237			`LD_DP <= '1';`
238			`LD_INSTR <= '1';`
239			`DECODING <= '0';`
240
241			`WHEN S_DECODE =>`
242			`PC_SRC <= "001";`
243			`LD_PC <= '1';`
244			`LD_IR <= '1';`
245			`LD_DP <= '1';`
246			`LD_INSTR <= '1';`
247			`DECODING <= '1';`
248
249			`WHEN S_UOP_P1 =>`
250			`LD_REG_A <= '1';`
251
252			`WHEN S_UOP_P2 =>`
253			`REG_SRC <= "000";`
254			`REG_WR <= '1';`
255
256			`PC_SRC <= "001";`
257			`LD_PC <= '1';`
258			`LD_IR <= '1';`
259			`LD_DP <= '1';`
260			`LD_INSTR <= '1';`
261			`DECODING <= '1';`
262
263			`WHEN S_BOP_P1 =>`
264			`LD_REG_A <= '1';`
265			`LD_REG_B <= '1';`
266
267			`WHEN S_BOP_P2 =>`
268			`REG_SRC <= "000";`
269			`REG_WR <= '1';`
270
271			`PC_SRC <= "001";`
272			`LD_PC <= '1';`
273			`LD_IR <= '1';`
274			`LD_DP <= '1';`
275			`LD_INSTR <= '1';`
276			`DECODING <= '1';`
277
278			`WHEN S_LD_RR =>`
279			`LD_REG_B <= '1';`
280
281			`WHEN S_LD_RR_2 =>`
282			`REG_SRC <= "000";`
283			`REG_WR <= '1';`
284
285			`PC_SRC <= "001";`
286			`LD_PC <= '1';`
287			`LD_IR <= '1';`
288			`LD_DP <= '1';`
289			`LD_INSTR <= '1';`
290			`DECODING <= '1';`
291
292			`WHEN S_LD_RV =>`
293			`PC_SRC <= "001";`
294			`LD_PC <= '1';`
295			`LD_IR <= '1';`
296			`LD_DP <= '0';`
297
298			`WHEN S_LD_RV_2 =>`
299			`REG_SRC <= "010";`
300			`REG_WR <= '1';`
301
302			`PC_SRC <= "001";`
303			`LD_PC <= '1';`
304			`LD_IR <= '1';`
305			`LD_DP <= '1';`
306			`LD_INSTR <= '1';`
307			`DECODING <= '1';`
308
309			`-- Write data from reg A to address reg B`
310			`WHEN S_LD_MR =>`
311			`LD_MAR <= '1';`
312			`LD_MDR <= '1';`
313
314			`WHEN S_LD_MR_2 =>`
315			`MEM_WR <= '1';`
316
317			`PC_SRC <= "001";`
318			`LD_PC <= '1';`
319			`LD_IR <= '1';`
320			`LD_DP <= '1';`
321			`LD_INSTR <= '1';`
322			`DECODING <= '1';`
323
324			`WHEN S_LD_RM =>`
325			`LD_MAR <= '1';`
326
327			`WHEN S_LD_RM_2 =>`
328			`REG_SRC <= "001";`
329			`REG_WR <= '1';`
330
331			`PC_SRC <= "001";`
332			`LD_PC <= '1';`
333			`LD_IR <= '1';`
334			`LD_DP <= '1';`
335			`LD_INSTR <= '1';`
336			`DECODING <= '1';`
337
338			`WHEN S_JZ_P0 =>`
339			`WHEN S_JNZ_P0 =>`
340			`NULL;`
341
342			`WHEN S_JZ_P1 =>`
343			`IF ZERO = '1' THEN`
344			`PC_SRC <= "010";`
345			`ELSE`
346			`PC_SRC <= "001";`
347			`END IF;`
348
349			`LD_PC <= '1';`
350			`LD_IR <= '1';`
351			`LD_DP <= '0';`
352
353			`WHEN S_JZ_P2 =>`
354			`PC_SRC <= "001";`
355			`LD_PC <= '1';`
356			`LD_IR <= '1';`
357			`LD_DP <= '1';`
358			`LD_INSTR <= '1';`
359			`DECODING <= '1';`
360
361			`WHEN S_JNZ_P1 =>`
362			`IF ZERO = '0' THEN`
363			`PC_SRC <= "010";`
364			`ELSE`
365			`PC_SRC <= "001";`
366			`END IF;`
367
368			`LD_PC <= '1';`
369			`LD_IR <= '1';`
370			`LD_DP <= '0';`
371
372			`WHEN S_JNZ_P2 =>`
373			`PC_SRC <= "001";`
374			`LD_PC <= '1';`
375			`LD_IR <= '1';`
376			`LD_DP <= '1';`
377			`LD_INSTR <= '1';`
378			`DECODING <= '1';`
379			`WHEN S_HALT =>`
380			`NULL;`
381
382			`WHEN OTHERS =>`
383			`PC_SRC <= "001";`
384			`LD_PC <= '1';`
385			`LD_IR <= '1';`
386			`LD_DP <= '1';`
387
388			`END CASE;`
389
390			`CASE IR_IN(15 DOWNTO 12) IS`
391			`WHEN "0001" =>`
392			`IF DECODING = '1' THEN`
393			`PC_SRC <= "111";`
394			`LD_PC <= '1';`
395			`END IF;`
396
397			`WHEN "0011" =>`
398			`WHEN "1001" =>`
399			`WHEN "1010" =>`
400			`IF DECODING = '1' THEN`
401			`LD_IR <= '0';`
402			`END IF;`
403
404			`WHEN OTHERS =>`
405			`NULL;`
406			`END CASE;`
407
408			`END PROCESS OUT1;`
409
410			`END ARCHITECTURE Mealy;`