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dgisselq |
################################################################################
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##
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## Filename:
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##
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## Project: XuLA2 board
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##
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## Purpose:
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##
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2015, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## License: GPL, v3, as defined and found on www.gnu.org,
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## http:##www.gnu.org/licenses/gpl.html
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##
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##
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################################################################################
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##
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##
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dgisselq |
.PHONY: all
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all: datestamp verilated bit
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# Could also depend upon load, if desired, but not necessary
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BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
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RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
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NOTES := `find . -name "*.txt"` `find . -name "*.html"`
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SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
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`find sw -name "*.sh"` `find sw -name "*.py"` \
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`find sw -name "*.pl"` `find sw -name Makefile`
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PROJ := xilinx/xula.prj xilinx/xula.xise xilinx/xula.xst \
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xilinx/xula.ut xilinx/Makefile
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BIN := `find xilinx -name "*.bit"`
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CONSTRAINTS := xula.ucf
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YYMMDD:=`date +%Y%m%d`
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datestamp: $(YYMMDD)-build.v
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$(YYMMDD)-build.v:
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-rm -rf 2*-build.v
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perl xilinx/mkdatev.pl > $(YYMMDD)-build.v
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cd rtl; ln -fs ../$(YYMMDD)-build.v builddate.v
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.PHONY: archive
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archive:
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tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
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.PHONY: tare
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tare:
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echo tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
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.PHONY: verilated
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verilated:
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cd rtl ; make
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.PHONY: bit
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bit:
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cd xilinx ; make xula.bit
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.PHONY: load
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load: bit
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xsload -b xula2-lx25 --fpga xilinx/xula.bit
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.PHONY: xload
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xload:
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xsload -b xula2-lx25 --fpga xilinx/toplevel.bit
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.PHONY: timing
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timing:
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cd xilinx ; make timing
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