OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [cfgtest.s] - Blame information for rev 84

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    cfgtest.s
4
//
5
// Project:     XuLA2 board
6
//
7
// Purpose:     To test whether or not the SPARTAN6_ICAPE interface works with
8
//              the wbicape6.v / wbicapesimple.v modules.
9
//
10
//      Normally, I'd do this test using wbregs only.  In this case, that's
11
//      not possible.  wbregs requires the use of the JTAG port for the XuLA
12
//      board.  Further, JTAG and ICAPE cannot be used at the same time.  So
13
//      our goal instead will be to use wbregs and ziprun to start this program,
14
//      to disconnect (i.e. stop using wbregs and ziprun, just leaving the CPU
15
//      to run), to wait for an RTC alarm, to trigger the configuration port
16
//      scope, and then to see how we did.  That's a lot, but doing things in
17
//      order is what a CPU is for--so let's see how we do.
18
//
19
//
20
// Creator:     Dan Gisselquist, Ph.D.
21
//              Gisselquist Technology, LLC
22
//
23
////////////////////////////////////////////////////////////////////////////////
24
//
25
// Copyright (C) 2015, Gisselquist Technology, LLC
26
//
27
// This program is free software (firmware): you can redistribute it and/or
28
// modify it under the terms of  the GNU General Public License as published
29
// by the Free Software Foundation, either version 3 of the License, or (at
30
// your option) any later version.
31
//
32
// This program is distributed in the hope that it will be useful, but WITHOUT
33
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
34
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
35
// for more details.
36
//
37
// License:     GPL, v3, as defined and found on www.gnu.org,
38
//              http://www.gnu.org/licenses/gpl.html
39
//
40
//
41
////////////////////////////////////////////////////////////////////////////////
42
//
43
//
44
#include "dev.i"
45
#include "sys.i"
46
master_entry:
47
        BRA     end_of_data
48
external_data:
49
cfg_result:
50
        WORD    0
51
status:
52
        WORD    0
53
end_of_data:
54
        ; Set up our stacks--though I don't think we'll need them
55
        MOV     sys_stack(PC),SP
56
        MOV     user_stack(PC),uSP
57
        ;
58
        ; Clear our registers
59
        CLR     R0
60
        CLR     R1
61
        CLR     R2
62
        CLR     R3
63
        CLR     R4
64
        CLR     R5
65
        CLR     R6
66
        CLR     R7
67
        CLR     R8
68
        CLR     R9
69
        CLR     R10
70
        CLR     R11
71
        MOV     R0,uR0
72
        MOV     R0,uR1
73
        MOV     R0,uR2
74
        MOV     R0,uR3
75
        MOV     R0,uR4
76
        MOV     R0,uR5
77
        MOV     R0,uR6
78
        MOV     R0,uR7
79
        MOV     R0,uR8
80
        MOV     R0,uR9
81
        MOV     R0,uR10
82
        MOV     R0,uR12
83
 
84
        ;
85
        ; Reset and prime our scope
86
        LDI     dev.cfgscope,R12
87
        LDI     0x03fc,R0
88
        STO     R0,(R12)
89
        ;
90
        ; Wait on an alarm
91
        LDI     sys.bus,R12
92
        LDI     0x7fffffff,R0           // Clear and disable all interrupts
93
        STO     R0,(R12)
94
        ; LDI   RTCINTEN|0x0ffff,R0     // Enable the RTC interrupt
95
        LDI     0x8080ffff,R0
96
        STO     R0,(R12)
97
        ;
98
        MOV     user_idle(PC),uPC
99
        RTU
100
        ;
101
        LDI     0x0080ffff,R0
102
        STO     R0,(R12)
103
        ;
104
        MOV     user_entry(PC),uPC
105
        MOV     user_stack(PC),uSP
106
        ;
107
        RTU
108
        ;
109
        HALT
110
        HALT
111
        BUSY
112
        HALT
113
 
114
user_idle:
115
        WAIT
116
        BRA     user_idle
117
 
118
user_entry:
119
        LDI     dev.cfg,R1
120
        LOD     (R1),R0
121
        ADD     5,R0
122
        STO     R0,cfg_result(PC)
123
        LDI     14,R0
124
        LDI     dev.cfg.cmd,R1
125
        STO     R0,(R1)
126
        NOOP
127
        TRAP    0
128
 
129
user_end_of_stack:
130
        FILL    512,0
131
user_stack:
132
sys_end_of_stack:
133
        FILL    512,0
134
sys_stack:
135
        WORD    0
136
 
137
;
138
;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.