URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: genlrs.S
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//
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// Project: XuLA2 board
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//
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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entry:
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; ; R0 -- used by test_lrs
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; ; R1 -- used by test_lrs
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; ; R2 -- used by test_lrs
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; ; R3 = return address
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LDI 0x80000000,R4 ; Taps
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LDI 0x00800000,R6 ; Current Memory Address
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MOV R6,R7 ; Start of memory
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LDI 0x00ffffff,R8 ; End of memory
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test_next_lrs:
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MOV __HERE__+2(PC),R3
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BRA test_lrs
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CMP 0,R0
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BGE next_tap_set
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STO R0,(R6)
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ADD 1,R6
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AND R8,R6
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OR R7,R6
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next_tap_set:
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ADD 1,R4
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BNZ test_next_lrs
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HALT
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test_lrs:
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; R0 = taps on entry
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; R0 = length on return
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; R3 = return PC address
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CLR R1 ; R1 will be our length
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LDI 1,R2 ; R2 will be our fill
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test_lrs_loop:
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LSR 1,R2
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XOR.C R0,R2
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ADD 1,R1
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CMP 1,R2
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BNZ test_lrs_loop
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MOV R1,R0
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MOV R3,PC
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