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[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [genlrs.S] - Blame information for rev 5

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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    genlrs.S
//
// Project:     XuLA2 board
//
// Purpose:
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
entry:
        ;                               ; R0 -- used by test_lrs
        ;                               ; R1 -- used by test_lrs
        ;                               ; R2 -- used by test_lrs
        ;                               ; R3 = return address
        LDI     0x80000000,R4           ; Taps
        LDI     0x00800000,R6           ; Current Memory Address
        MOV     R6,R7                   ; Start of memory
        LDI     0x00ffffff,R8           ; End of memory
 
test_next_lrs:
        MOV     __HERE__+2(PC),R3
        BRA     test_lrs
        CMP     0,R0
        BGE     next_tap_set
        STO     R0,(R6)
        ADD     1,R6
        AND     R8,R6
        OR      R7,R6
next_tap_set:
        ADD     1,R4
        BNZ     test_next_lrs
        HALT
 
test_lrs:
        ; R0 = taps on entry
        ; R0 = length on return
        ; R3 = return PC address
        CLR     R1      ;       R1 will be our length
        LDI     1,R2    ;       R2 will be our fill
test_lrs_loop:
        LSR     1,R2
        XOR.C   R0,R2
        ADD     1,R1
        CMP     1,R2
        BNZ     test_lrs_loop
        MOV     R1,R0
 
        MOV     R3,PC

Line No.	Rev	Author	Line
1	4	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: genlrs.S`
4			`//`
5			`// Project: XuLA2 board`
6			`//`
7			`// Purpose:`
8			`//`
9			`//`
10			`// Creator: Dan Gisselquist, Ph.D.`
11			`// Gisselquist Technology, LLC`
12			`//`
13			`////////////////////////////////////////////////////////////////////////////////`
14			`//`
15			`// Copyright (C) 2015, Gisselquist Technology, LLC`
16			`//`
17			`// This program is free software (firmware): you can redistribute it and/or`
18			`// modify it under the terms of the GNU General Public License as published`
19			`// by the Free Software Foundation, either version 3 of the License, or (at`
20			`// your option) any later version.`
21			`//`
22			`// This program is distributed in the hope that it will be useful, but WITHOUT`
23			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
24			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
25			`// for more details.`
26			`//`
27			`// License: GPL, v3, as defined and found on www.gnu.org,`
28			`// http://www.gnu.org/licenses/gpl.html`
29			`//`
30			`//`
31			`////////////////////////////////////////////////////////////////////////////////`
32			`//`
33			`//`
34			`entry:`
35			`; ; R0 -- used by test_lrs`
36			`; ; R1 -- used by test_lrs`
37			`; ; R2 -- used by test_lrs`
38			`; ; R3 = return address`
39			`LDI 0x80000000,R4 ; Taps`
40			`LDI 0x00800000,R6 ; Current Memory Address`
41			`MOV R6,R7 ; Start of memory`
42			`LDI 0x00ffffff,R8 ; End of memory`
43
44			`test_next_lrs:`
45			`MOV __HERE__+2(PC),R3`
46			`BRA test_lrs`
47			`CMP 0,R0`
48			`BGE next_tap_set`
49			`STO R0,(R6)`
50			`ADD 1,R6`
51			`AND R8,R6`
52			`OR R7,R6`
53			`next_tap_set:`
54			`ADD 1,R4`
55			`BNZ test_next_lrs`
56			`HALT`
57
58			`test_lrs:`
59			`; R0 = taps on entry`
60			`; R0 = length on return`
61			`; R3 = return PC address`
62			`CLR R1 ; R1 will be our length`
63			`LDI 1,R2 ; R2 will be our fill`
64			`test_lrs_loop:`
65			`LSR 1,R2`
66			`XOR.C R0,R2`
67			`ADD 1,R1`
68			`CMP 1,R2`
69			`BNZ test_lrs_loop`
70			`MOV R1,R0`
71
72			`MOV R3,PC`

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[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [genlrs.S] - Blame information for rev 5