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[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [memtest.s] - Blame information for rev 15

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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    memtest.S
//
// Project:     XuLA2 board
//
// Purpose:     To test whether or not we can interface with the SDRAM on the
//              XuLA2 board.
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#define LFSRFILL        0x000001
// #define      LFSRTAPS        0x004597f
#define LFSRTAPS        0x0408b85
#define SDRAMBASE       0x0800000
// #define      SDRAMLEN        0x0800000
#define SDRAMLEN        0x0800000
#define RAMSCOPE        0x011c
#define ZIPSCOPE        0x011e
master_entry:
        MOV     user_entry(PC),uPC
        ; LDI   RAMSCOPE,R8
        ; LDI   0x04000000,R9
        ; STO   R9,(R8)
        RTU
        ; // Capture what just happened
        ; LDI   0x8c000000,R9
        ; STO   R9,(R8)
        ; NOP
        ; 
        HALT
 
user_entry:
// #define      CLEAR_MEMORY
#ifdef  CLEAR_MEMORY
clear_memory:
        LDI     SDRAMBASE,R0
        LDI     SDRAMLEN,R1
        ADD     R0,R1
        CLR     R2
clear_memory_loop:
        STO     R2,(R0)
        ADD     1,R0
        CMP     R0,R1
        BGT     clear_memory_loop
end_clear_memory:
#endif
 
        LDI     LFSRFILL,R2
        LDI     LFSRTAPS,R3
        CLR     R12
 
write_test:
        LDI     SDRAMBASE,R0
        LDI     SDRAMLEN,R1
        MOV     R2,R7           ; Copy our initial fill
        CMP     0,R2
        HALT.Z
// #define      WAIT_FOR_WRITE_SCOPE
#ifdef  WAIT_FOR_WRITE_SCOPE
        LDI     RAMSCOPE,R8
        LDI     0x01ffc,R9
        STO     R9,(R8)                 ; Reset the SDRAM scope
        NOP                             ; Give it a chance to reset
        LDI     0x10000000,R10
scope_not_ready:
        NOP
        LOD     (R8),R9
        TST     R10,R9
        BZ      scope_not_ready
#endif
 
write_test_loop:
        LSR     1,R2
        XOR.C   R3,R2
        MOV     R2,R4
 
        LSR     1,R2
        XOR.C   R3,R2
        MOV     R2,R5
 
        LSR     1,R2
        XOR.C   R3,R2           ; wr_reg_ce = R2
 
        STO     R4,(R0)         ; op = R4
        STO     R5,1(R0)        ; dcdA = R5
        STO     R2,2(R0)        ; instruction - R2
        ADD     3,R0
        SUB     3,R1
        CMP     3,R1
        BGE     write_test_loop
 
read_test:
        LDI     SDRAMBASE,R0
        LDI     SDRAMLEN,R1
// #define      WAIT_FOR_READ_SCOPE
#ifdef  WAIT_FOR_READ_SCOPE
        LDI     RAMSCOPE,R8
        LDI     0x01ffc,R9
        STO     R9,(R8)                 ; Reset the SDRAM scope
        NOP                             ; Give it a chance to reset
        LDI     0x10000000,R10
not_ready:
        NOP
        LOD     (R8),R9
        TST     R10,R9
        BZ      not_ready
#endif
//
//      RAM[49072] = 0x02b39ba ... not RAM[0].  What's going on here?
//
read_test_loop:
        LOD     (R0),R4
        LOD     1(R0),R5
        LOD     2(R0),R6
 
        LSR     1,R7
        XOR.C   R3,R7
        CMP     R7,R4
        TRAP.NZ 0
 
        LSR     1,R7
        XOR.C   R3,R7
        CMP     R7,R5
        TRAP.NZ 0
 
        LSR     1,R7
        XOR.C   R3,R7
        CMP     R7,R6
        TRAP.NZ 0
 
        ADD     3,R0
        SUB     3,R1
        CMP     3,R1
 
        BGE     read_test_loop
 
        ADD     1,R12
        BRA     write_test
;
;
;
;       0x0408b85
;       0x060ce47
;       0x070eca6
;       0x0387653
;       0x05cb0ac
;       0x02e5856
;       0x0172c2b
;       0x04b1d90
;       0x0258ec8
;       0x012c764
;       0x00963b2
;       0x004b1d9
;       0x042d369
;       0x061e231
;       0x0707a9d
;       ...
;
;

Line No.	Rev	Author	Line
1	10	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: memtest.S`
4			`//`
5			`// Project: XuLA2 board`
6			`//`
7			`// Purpose: To test whether or not we can interface with the SDRAM on the`
8			`// XuLA2 board.`
9			`//`
10			`//`
11			`// Creator: Dan Gisselquist, Ph.D.`
12			`// Gisselquist Technology, LLC`
13			`//`
14			`////////////////////////////////////////////////////////////////////////////////`
15			`//`
16			`// Copyright (C) 2015, Gisselquist Technology, LLC`
17			`//`
18			`// This program is free software (firmware): you can redistribute it and/or`
19			`// modify it under the terms of the GNU General Public License as published`
20			`// by the Free Software Foundation, either version 3 of the License, or (at`
21			`// your option) any later version.`
22			`//`
23			`// This program is distributed in the hope that it will be useful, but WITHOUT`
24			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
25			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
26			`// for more details.`
27			`//`
28			`// License: GPL, v3, as defined and found on www.gnu.org,`
29			`// http://www.gnu.org/licenses/gpl.html`
30			`//`
31			`//`
32			`////////////////////////////////////////////////////////////////////////////////`
33			`//`
34			`//`
35			`#define LFSRFILL 0x000001`
36			`// #define LFSRTAPS 0x004597f`
37			`#define LFSRTAPS 0x0408b85`
38			`#define SDRAMBASE 0x0800000`
39			`// #define SDRAMLEN 0x0800000`
40			`#define SDRAMLEN 0x0800000`
41			`#define RAMSCOPE 0x011c`
42			`#define ZIPSCOPE 0x011e`
43			`master_entry:`
44			`MOV user_entry(PC),uPC`
45			`; LDI RAMSCOPE,R8`
46			`; LDI 0x04000000,R9`
47			`; STO R9,(R8)`
48			`RTU`
49			`; // Capture what just happened`
50			`; LDI 0x8c000000,R9`
51			`; STO R9,(R8)`
52			`; NOP`
53			`;`
54			`HALT`
55
56			`user_entry:`
57			`// #define CLEAR_MEMORY`
58			`#ifdef CLEAR_MEMORY`
59			`clear_memory:`
60			`LDI SDRAMBASE,R0`
61			`LDI SDRAMLEN,R1`
62			`ADD R0,R1`
63			`CLR R2`
64			`clear_memory_loop:`
65			`STO R2,(R0)`
66			`ADD 1,R0`
67			`CMP R0,R1`
68			`BGT clear_memory_loop`
69			`end_clear_memory:`
70			`#endif`
71
72			`LDI LFSRFILL,R2`
73			`LDI LFSRTAPS,R3`
74			`CLR R12`
75
76			`write_test:`
77			`LDI SDRAMBASE,R0`
78			`LDI SDRAMLEN,R1`
79			`MOV R2,R7 ; Copy our initial fill`
80			`CMP 0,R2`
81			`HALT.Z`
82			`// #define WAIT_FOR_WRITE_SCOPE`
83			`#ifdef WAIT_FOR_WRITE_SCOPE`
84			`LDI RAMSCOPE,R8`
85			`LDI 0x01ffc,R9`
86			`STO R9,(R8) ; Reset the SDRAM scope`
87			`NOP ; Give it a chance to reset`
88			`LDI 0x10000000,R10`
89			`scope_not_ready:`
90			`NOP`
91			`LOD (R8),R9`
92			`TST R10,R9`
93			`BZ scope_not_ready`
94			`#endif`
95
96			`write_test_loop:`
97			`LSR 1,R2`
98			`XOR.C R3,R2`
99			`MOV R2,R4`
100
101			`LSR 1,R2`
102			`XOR.C R3,R2`
103			`MOV R2,R5`
104
105			`LSR 1,R2`
106			`XOR.C R3,R2 ; wr_reg_ce = R2`
107
108			`STO R4,(R0) ; op = R4`
109			`STO R5,1(R0) ; dcdA = R5`
110			`STO R2,2(R0) ; instruction - R2`
111			`ADD 3,R0`
112			`SUB 3,R1`
113			`CMP 3,R1`
114			`BGE write_test_loop`
115
116			`read_test:`
117			`LDI SDRAMBASE,R0`
118			`LDI SDRAMLEN,R1`
119			`// #define WAIT_FOR_READ_SCOPE`
120			`#ifdef WAIT_FOR_READ_SCOPE`
121			`LDI RAMSCOPE,R8`
122			`LDI 0x01ffc,R9`
123			`STO R9,(R8) ; Reset the SDRAM scope`
124			`NOP ; Give it a chance to reset`
125			`LDI 0x10000000,R10`
126			`not_ready:`
127			`NOP`
128			`LOD (R8),R9`
129			`TST R10,R9`
130			`BZ not_ready`
131			`#endif`
132			`//`
133			`// RAM[49072] = 0x02b39ba ... not RAM[0]. What's going on here?`
134			`//`
135			`read_test_loop:`
136			`LOD (R0),R4`
137			`LOD 1(R0),R5`
138			`LOD 2(R0),R6`
139
140			`LSR 1,R7`
141			`XOR.C R3,R7`
142			`CMP R7,R4`
143			`TRAP.NZ 0`
144
145			`LSR 1,R7`
146			`XOR.C R3,R7`
147			`CMP R7,R5`
148			`TRAP.NZ 0`
149
150			`LSR 1,R7`
151			`XOR.C R3,R7`
152			`CMP R7,R6`
153			`TRAP.NZ 0`
154
155			`ADD 3,R0`
156			`SUB 3,R1`
157			`CMP 3,R1`
158
159			`BGE read_test_loop`
160
161			`ADD 1,R12`
162			`BRA write_test`
163			`;`
164			`;`
165			`;`
166			`; 0x0408b85`
167			`; 0x060ce47`
168			`; 0x070eca6`
169			`; 0x0387653`
170			`; 0x05cb0ac`
171			`; 0x02e5856`
172			`; 0x0172c2b`
173			`; 0x04b1d90`
174			`; 0x0258ec8`
175			`; 0x012c764`
176			`; 0x00963b2`
177			`; 0x004b1d9`
178			`; 0x042d369`
179			`; 0x061e231`
180			`; 0x0707a9d`
181	15	dgisselq	`; ...`
182	10	dgisselq	`;`
183			`;`

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[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [memtest.s] - Blame information for rev 15