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dgisselq |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename: sys.i
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;
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; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose: This is the beginnings of a system wide header file for the
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; Zip System. It describes and declares the peripherals
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; that will the be used and referenced by the assembly files.
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;
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; Status: As of August, 2015, I have no confidence that the preprocessor
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; can properly include this file. It certainly cannot handle
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; macros (yet).
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;
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; Creator: Dan Gisselquist, Ph.D.
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; Gisselquist Technology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; License: GPL, v3, as defined and found on www.gnu.org,
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; http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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sys.bus equ 0xc0000000
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sys.breaken equ 0x080
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sys.step equ 0x040
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sys.gie equ 0x020
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sys.sleep equ 0x010
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sys.ccv equ 0x008
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sys.ccn equ 0x004
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sys.ccc equ 0x002
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sys.ccz equ 0x001
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sys.bus.pic equ 0x000
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sys.bus.wdt equ 0x001
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sys.bus.wdbus equ 0x002
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sys.bus.apic equ 0x003
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sys.bus.tma equ 0x004
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sys.bus.tmb equ 0x005
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sys.bus.tmc equ 0x006
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sys.bus.jiffies equ 0x007
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sys.mctr.task equ 0x008
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sys.mctr.mstl equ 0x009
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sys.mctr.pstl equ 0x00a
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sys.mctr.icnt equ 0x00b
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sys.uctr.task equ 0x00c
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sys.uctr.mstl equ 0x00d
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sys.uctr.pstl equ 0x00e
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sys.uctr.icnt equ 0x00f
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sys.dma equ 0x010
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; Define the location(s) of our peripherals,
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#define sys.base 0xc0000000
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#struct sys
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pic
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wdt
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cache
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ctrpic
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tma
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tmb
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tmc
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jiffies
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mtask
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mstl
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mpstl
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mastl
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utask
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ustl
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upstl
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uastl
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#endstruct
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; and their associated interrupt vectors ...
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#define DMAINT 0x0001
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#define JIFFYINT 0x0002 ;
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#define TMCINT 0x0004 ;
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#define TMBINT 0x0008 ;
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#define TMAINT 0x0010 ;
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#define CTRPICINT 0x0020 ; The aux interrupt controller
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#define RTCINT 0x0080 ;
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#define FLASHINT 0x0100 ;
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#define SCOPINT 0x0200 ;
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#define GPIOINT 0x0400 ;
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#define PWMINT 0x0800 ;
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#define RXUARTINT 0x1000 ;
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#define TXUARTINT 0x2000 ;
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; Masks to send to enable those same vectors
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#define ENABLE_INTS 0x80000000
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#define DMAINTEN (ENABLE_INTS|(DMAINT<<16))
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#define JIFFYINTEN (ENABLE_INTS|(JIFFYINT<<16))
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#define TMCINTEN (ENABLE_INTS|(TMCINT<<16))
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#define TMBINTEN (ENABLE_INTS|(TMBINT<<16))
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#define TMAINTEN (ENABLE_INTS|(TMAINT<<16))
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#define CTRPICEN (ENABLE_INTS|(CTRPICINT<<16))
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#define RTCINTEN (ENABLE_INTS|(RTCINT<<16))
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#define FLASHINTEN (ENABLE_INTS|(FLASHINT<<16))
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#define SCOPINTEN (ENABLE_INTS|(SCOPINT<<16))
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#define GPIOINTEN (ENABLE_INTS|(GPIOINT<<16))
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#define PWMINTEN (ENABLE_INTS|(PWMINT<<16))
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#define RXUARTINTEN (ENABLE_INTS|(RXUARTINT<<16))
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#define TXUARTINTEN (ENABLE_INTS|(TXUARTINT<<16))
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; And similar masks to disable them
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#define DMAINTDIS (DMAINT<<16)
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#define JIFFYINTDIS (JIFFYINT<<16)
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#define TMCINTDIS (TMCINT<<16)
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#define TMBINTDIS (TMBINT<<16)
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#define TMAINTDIS (TMAINT<<16)
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#define CTRPICDIS (ENABLE_INTS|(CTRPICINT<<16)
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#define RTCINTDIS (RTCINT<<16)
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#define FLASHINTDIS (FLASHINT<<16)
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#define SCOPINTDIS (SCOPINT<<16)
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#define GPIOINTDIS (GPIOINT<<16)
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#define PWMINTDIS (PWMINT<<16)
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#define RXUARTINTDIS (RXUARTINT<<16)
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#define TXUARTINTDIS (TXUARTINT<<16)
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; Define our condition code bits
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#define CCZ 0x001
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#define CCC 0x002
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#define CCN 0x004
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#define CCV 0x008
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#define CCSLEEP 0x010
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#define CCGIE 0x020
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#define CCSTEP 0x040
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#define CCUBRK 0x080
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#define FJSR(LBL,RG) MOV __here__+2(PC),RG \
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BRA LBL
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#define FRET(RG) JMP RG
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