Subversion Repositories xulalx25soc

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;

; Filename:     sys.i

;

; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core

;

; Purpose:      This is the beginnings of a system wide header file for the

;               Zip System.   It describes and declares the peripherals

;               that will the be used and referenced by the assembly files.

;

; Status:       As of August, 2015, I have no confidence that the preprocessor

;               can properly include this file.  It certainly cannot handle

;               macros (yet).

;

; Creator:      Dan Gisselquist, Ph.D.

;               Gisselquist Technology, LLC

;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;

; Copyright (C) 2015, Gisselquist Technology, LLC

;

; This program is free software (firmware): you can redistribute it and/or

; modify it under the terms of  the GNU General Public License as published

; by the Free Software Foundation, either version 3 of the License, or (at

; your option) any later version.

;

; This program is distributed in the hope that it will be useful, but WITHOUT

; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

; for more details.

;

; License:      GPL, v3, as defined and found on www.gnu.org,

;               http://www.gnu.org/licenses/gpl.html

;

;

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;

        sys.bus         equ     0xc0000000

        sys.breaken     equ     0x080

        sys.step        equ     0x040

        sys.gie         equ     0x020

        sys.sleep       equ     0x010

        sys.ccv         equ     0x008

        sys.ccn         equ     0x004

        sys.ccc         equ     0x002

        sys.ccz         equ     0x001

        sys.bus.pic     equ     0x000

        sys.bus.wdt     equ     0x001

        sys.bus.wdbus   equ     0x002

        sys.bus.apic    equ     0x003

        sys.bus.tma     equ     0x004

        sys.bus.tmb     equ     0x005

        sys.bus.tmc     equ     0x006

        sys.bus.jiffies equ     0x007

        sys.mctr.task   equ     0x008

        sys.mctr.mstl   equ     0x009

        sys.mctr.pstl   equ     0x00a

        sys.mctr.icnt   equ     0x00b

        sys.uctr.task   equ     0x00c

        sys.uctr.mstl   equ     0x00d

        sys.uctr.pstl   equ     0x00e

        sys.uctr.icnt   equ     0x00f

        sys.dma         equ     0x010

; Define the location(s) of our peripherals,

#define sys.base        0xc0000000

#struct sys

        pic

        wdt

        cache

        ctrpic

        tma

        tmb

        tmc

        jiffies

        mtask

        mstl

        mpstl

        mastl

        utask

        ustl

        upstl

        uastl

#endstruct

; and their associated interrupt vectors ...

#define DMAINT          0x0001

#define JIFFYINT        0x0002  ;

#define TMCINT          0x0004  ;

#define TMBINT          0x0008  ;

#define TMAINT          0x0010  ;

#define CTRPICINT       0x0020  ; The aux interrupt controller

#define RTCINT          0x0080  ;

#define FLASHINT        0x0100  ;

#define SCOPINT         0x0200  ;

#define GPIOINT         0x0400  ;

#define PWMINT          0x0800  ;

#define RXUARTINT       0x1000  ;

#define TXUARTINT       0x2000  ;

; Masks to send to enable those same vectors

#define ENABLE_INTS     0x80000000

#define DMAINTEN        (ENABLE_INTS|(DMAINT<<16))

#define JIFFYINTEN      (ENABLE_INTS|(JIFFYINT<<16))

#define TMCINTEN        (ENABLE_INTS|(TMCINT<<16))

#define TMBINTEN        (ENABLE_INTS|(TMBINT<<16))

#define TMAINTEN        (ENABLE_INTS|(TMAINT<<16))

#define CTRPICEN        (ENABLE_INTS|(CTRPICINT<<16))

#define RTCINTEN        (ENABLE_INTS|(RTCINT<<16))

#define FLASHINTEN      (ENABLE_INTS|(FLASHINT<<16))

#define SCOPINTEN       (ENABLE_INTS|(SCOPINT<<16))

#define GPIOINTEN       (ENABLE_INTS|(GPIOINT<<16))

#define PWMINTEN        (ENABLE_INTS|(PWMINT<<16))

#define RXUARTINTEN     (ENABLE_INTS|(RXUARTINT<<16))

#define TXUARTINTEN     (ENABLE_INTS|(TXUARTINT<<16))

; And similar masks to disable them

#define DMAINTDIS       (DMAINT<<16)

#define JIFFYINTDIS     (JIFFYINT<<16)

#define TMCINTDIS       (TMCINT<<16)

#define TMBINTDIS       (TMBINT<<16)

#define TMAINTDIS       (TMAINT<<16)

#define CTRPICDIS       (ENABLE_INTS|(CTRPICINT<<16)

#define RTCINTDIS       (RTCINT<<16)

#define FLASHINTDIS     (FLASHINT<<16)

#define SCOPINTDIS      (SCOPINT<<16)

#define GPIOINTDIS      (GPIOINT<<16)

#define PWMINTDIS       (PWMINT<<16)

#define RXUARTINTDIS    (RXUARTINT<<16)

#define TXUARTINTDIS    (TXUARTINT<<16)

; Define our condition code bits

#define CCZ     0x001

#define CCC     0x002

#define CCN     0x004

#define CCV     0x008

#define CCSLEEP 0x010

#define CCGIE   0x020

#define CCSTEP  0x040

#define CCUBRK  0x080

#define FJSR(LBL,RG)    MOV __here__+2(PC),RG   \

                        BRA LBL

#define FRET(RG)        JMP     RG