OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [xulalink.x] - Blame information for rev 76

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 36 dgisselq
/*******************************************************************************
2
*
3
* Filename:     zipcmod.x
4
*
5
* Project:      XuLA2-LX25 SoC
6
*
7
* Purpose:      This script provides a description of the XuLA2-LX25 SoC,
8
*               and specifically the memory bus that the Zip CPU would see,
9
*               for the purposes of where to place memory when linking.
10
*
11
* Creator:      Dan Gisselquist, Ph.D.
12
*               Gisselquist Technology, LLC
13
*
14
********************************************************************************
15
*
16
* Copyright (C) 2016, Gisselquist Technology, LLC
17
*
18
* This program is free software (firmware): you can redistribute it and/or
19
* modify it under the terms of  the GNU General Public License as published
20
* by the Free Software Foundation, either version 3 of the License, or (at
21
* your option) any later version.
22
*
23
* This program is distributed in the hope that it will be useful, but WITHOUT
24
* ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
25
* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
26
* for more details.
27
*
28
* License:      GPL, v3, as defined and found on www.gnu.org,
29
*               http://www.gnu.org/licenses/gpl.html
30
*
31
*
32
*******************************************************************************/
33
 
34
ENTRY(_start)
35
 
36
MEMORY
37
{
38
        blkram (wx) : ORIGIN = 0x002000, LENGTH = 0x002000
39
        flash  (rx) : ORIGIN = 0x040000, LENGTH = 0x040000
40
        sdram  (wx) : ORIGIN = 0x800000, LENGTH = 0x800000
41
}
42
 
43
_top_of_stack = ORIGIN(blkram) + LENGTH(blkram) - 1;
44
 
45
SECTIONS
46
{
47
  . = 0x02000;
48
  .rocode 0x02000 : { *(.start) *(.text)
49
        *(.rodata)
50
        *(.strings) } > blkram
51
  .data : { *(.data) *(COMMON) *(.bss) } > blkram
52
  _top_of_heap = 0xf00000;
53
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.