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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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// Filename: busmaster_tb.cpp
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//
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// Project: FPGA library development (XuLA2 development board)
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//
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// Purpose: This is piped version of the testbench for the busmaster
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// verilog code. The busmaster code is designed to be a complete
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dgisselq |
// code set implementing all of the functionality of the XESS XuLA2
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// development board. If done well, the programs talking to this one
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// should be able to talk to the board and apply the same tests to the
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// board itself.
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dgisselq |
//
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dgisselq |
// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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dgisselq |
//
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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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dgisselq |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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dgisselq |
#include <signal.h>
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#include <time.h>
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#include "verilated.h"
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#include "Vbusmaster.h"
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#include "testb.h"
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// #include "twoc.h"
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#include "pipecmdr.h"
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#include "qspiflashsim.h"
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#include "sdramsim.h"
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dgisselq |
#include "sdspisim.h"
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dgisselq |
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#include "port.h"
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// Add a reset line, since Vbusmaster doesn't have one
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class Vbusmasterr : public Vbusmaster {
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public:
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int i_rst;
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virtual ~Vbusmasterr() {}
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};
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// No particular "parameters" need definition or redefinition here.
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class BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {
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public:
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unsigned long m_tx_busy_count;
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QSPIFLASHSIM m_flash;
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SDSPISIM m_sdcard;
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SDRAMSIM m_sdram;
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unsigned m_last_led;
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time_t m_start_time;
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bool m_last_writeout;
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BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) {
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m_start_time = time(NULL);
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}
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void reset(void) {
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m_core->i_clk = 1;
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m_core->eval();
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}
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dgisselq |
void setsdcard(const char *fn) {
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m_sdcard.load(fn);
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printf("LOADING SDCARD FROM: \'%s\'\n", fn);
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}
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void tick(void) {
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int flash_miso, sdcard_miso;
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if ((m_tickcount & ((1<<28)-1))==0) {
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double ticks_per_second = m_tickcount;
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time_t seconds_passed = time(NULL)-m_start_time;
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if (seconds_passed != 0) {
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ticks_per_second /= (double)(time(NULL) - m_start_time);
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printf(" ******** %.6f TICKS PER SECOND\n",
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ticks_per_second);
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}
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}
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// Set up the bus before any clock tick
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m_core->i_clk = 1;
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dgisselq |
flash_miso = (m_flash(m_core->o_sf_cs_n,
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m_core->o_spi_sck,
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m_core->o_spi_mosi)&0x02)?1:0;
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sdcard_miso = m_sdcard(m_core->o_sd_cs_n, m_core->o_spi_sck,
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m_core->o_spi_mosi);
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if ((m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))
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m_core->i_spi_miso = 1;
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else if ((!m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))
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m_core->i_spi_miso = flash_miso;
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else if ((m_core->o_sf_cs_n)&&(!m_core->o_sd_cs_n))
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m_core->i_spi_miso = sdcard_miso;
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else
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assert((m_core->o_sf_cs_n)||(m_core->o_sd_cs_n));
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m_core->i_ram_data = m_sdram(1,
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m_core->o_ram_cke, m_core->o_ram_cs_n,
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m_core->o_ram_ras_n, m_core->o_ram_cas_n,
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m_core->o_ram_we_n, m_core->o_ram_bs,
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m_core->o_ram_addr, m_core->o_ram_drive_data,
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m_core->o_ram_data);
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PIPECMDR::tick();
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bool writeout = false;
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/*
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if (m_core->v__DOT__sdram__DOT__r_pending)
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writeout = true;
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dgisselq |
else if (m_core->v__DOT__sdram__DOT__bank_active[0])
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writeout = true;
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dgisselq |
else if (m_core->v__DOT__sdram__DOT__bank_active[1])
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dgisselq |
writeout = true;
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dgisselq |
else if (m_core->v__DOT__sdram__DOT__bank_active[2])
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dgisselq |
writeout = true;
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dgisselq |
else if (m_core->v__DOT__sdram__DOT__bank_active[3])
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dgisselq |
writeout = true;
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*/
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dgisselq |
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dgisselq |
if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
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writeout = true;
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dgisselq |
/*
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if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
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writeout = true;
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if (m_core->v__DOT__genbus__DOT__exec_stb)
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writeout = true;
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*/
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dgisselq |
#define v__DOT__wb_addr v__DOT__dwb_addr
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#define v__DOT__dwb_stall v__DOT__wb_stall
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#define v__DOT__dwb_ack v__DOT__wb_ack
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#define v__DOT__wb_cyc v__DOT__dwb_cyc
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#define v__DOT__wb_stb v__DOT__dwb_stb
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#define v__DOT__wb_we v__DOT__dwb_we
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#define v__DOT__dwb_idata v__DOT__wb_idata
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#define v__DOT__wb_data v__DOT__dwb_odata
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dgisselq |
if (!m_core->v__DOT__zippy__DOT__cmd_halt)
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writeout = true;
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if (!m_core->o_sd_cs_n)
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writeout = true;
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else if (!m_core->v__DOT__sdcard_cs_n)
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writeout = true;
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else if ((((m_core->v__DOT__wb_addr ^ 0x0120)&(~0x03))==0)
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&&(m_core->v__DOT__wb_cyc))
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writeout = true;
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dgisselq |
/*
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dgisselq |
writeout = (writeout)||(m_core->i_rx_stb)
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||((m_core->o_tx_stb)&&(!m_core->i_tx_busy));
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writeout = (writeout)||(m_core->v__DOT____Vcellinp__genbus____pinNumber9);
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writeout = (writeout)||(m_core->v__DOT__wb_stb);
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writeout = (writeout)||(m_core->v__DOT__wb_err);
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dgisselq |
*/
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dgisselq |
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if ((writeout)||(m_last_writeout)) {
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dgisselq |
printf("%08lx:", m_tickcount);
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dgisselq |
/*
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printf("%d/%02x %d/%02x%s ",
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m_core->i_rx_stb, m_core->i_rx_data,
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m_core->o_tx_stb, m_core->o_tx_data,
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m_core->i_tx_busy?"/BSY":" ");
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*/
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printf("(%d,%d->%d),(%c:%d,%d->%d)|%c[%08x/%08x]@%08x %c%c%c",
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dgisselq |
m_core->v__DOT__wbu_cyc,
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m_core->v__DOT__dwb_cyc, // was zip_cyc
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m_core->v__DOT__wb_cyc,
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//
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dgisselq |
m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner?'Z':'j',
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dgisselq |
m_core->v__DOT__wbu_stb,
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// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
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m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
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m_core->v__DOT__wb_stb,
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//
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(m_core->v__DOT__wb_we)?'W':'R',
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m_core->v__DOT__wb_data,
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m_core->v__DOT__dwb_idata,
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m_core->v__DOT__wb_addr,
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dgisselq |
(m_core->v__DOT__dwb_ack)?'A':
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(m_core->v__DOT____Vcellinp__genbus____pinNumber9)?'a':' ',
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(m_core->v__DOT__dwb_stall)?'S':
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(m_core->v__DOT____Vcellinp__genbus____pinNumber10)?'s':' ',
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dgisselq |
(m_core->v__DOT__wb_err)?'E':'.');
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dgisselq |
printf(" RUNWB %d:%09lx %d@0x%08x %3x %3x %d %d/%d/%d %d:%09lx",
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m_core->v__DOT__genbus__DOT__fifo_in_stb,
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m_core->v__DOT__genbus__DOT__fifo_in_word,
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dgisselq |
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
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m_core->v__DOT__wbu_addr,
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m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
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m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed,
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m_core->v__DOT__genbus__DOT__runwb__DOT__w_eow,
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dgisselq |
m_core->v__DOT__genbus__DOT__runwb__DOT__last_read_request,
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dgisselq |
m_core->v__DOT__genbus__DOT__runwb__DOT__last_ack,
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m_core->v__DOT__genbus__DOT__runwb__DOT__zero_acks,
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m_core->v__DOT__genbus__DOT__exec_stb,
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m_core->v__DOT__genbus__DOT__exec_word);
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| 225 |
106 |
dgisselq |
printf(" WBU[%d,%3d,%3d]",
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m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
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m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
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m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed);
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| 230 |
75 |
dgisselq |
/*
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4 |
dgisselq |
printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
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| 232 |
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(m_core->v__DOT__sdram_sel)?'!':' ',
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m_core->o_ram_cs_n, m_core->o_ram_ras_n,
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m_core->o_ram_cas_n, m_core->o_ram_we_n,
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m_core->o_ram_bs, m_core->o_ram_data,
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| 236 |
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(m_core->o_ram_drive_data)?'D':'-',
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| 237 |
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m_core->o_ram_addr,
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| 238 |
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(m_core->o_ram_addr>>10)&1,
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| 239 |
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m_core->i_ram_data,
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| 240 |
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(m_core->o_ram_drive_data)?'-':'V');
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| 241 |
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| 242 |
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printf(" SD[%d,%d-%3x%d]",
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| 243 |
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m_core->v__DOT__sdram__DOT__r_state,
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| 244 |
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m_sdram.pwrup(),
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| 245 |
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m_core->v__DOT__sdram__DOT__refresh_clk,
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| 246 |
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m_core->v__DOT__sdram__DOT__need_refresh);
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| 247 |
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| 248 |
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printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
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| 249 |
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m_core->v__DOT__sdram__DOT__bank_active[0],
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| 250 |
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m_core->v__DOT__sdram__DOT__bank_row[0],
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| 251 |
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m_core->v__DOT__sdram__DOT__bank_active[1],
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| 252 |
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m_core->v__DOT__sdram__DOT__bank_row[1],
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| 253 |
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m_core->v__DOT__sdram__DOT__bank_active[2],
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| 254 |
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m_core->v__DOT__sdram__DOT__bank_row[2],
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| 255 |
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m_core->v__DOT__sdram__DOT__bank_active[3],
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| 256 |
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m_core->v__DOT__sdram__DOT__bank_row[3],
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| 257 |
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m_core->v__DOT__sdram__DOT__clocks_til_idle,
|
| 258 |
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m_core->v__DOT__sdram__DOT__r_barrell_ack);
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| 259 |
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| 260 |
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printf(" %s%s%c[%08x@%06x]",
|
| 261 |
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(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
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| 262 |
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(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
|
| 263 |
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(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
|
| 264 |
37 |
dgisselq |
(m_core->v__DOT__sdram__DOT__r_we)
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| 265 |
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?(m_core->v__DOT__sdram__DOT__r_data)
|
| 266 |
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:(m_core->v__DOT__sdram_data),
|
| 267 |
4 |
dgisselq |
(m_core->v__DOT__sdram__DOT__r_addr));
|
| 268 |
75 |
dgisselq |
*/
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| 269 |
4 |
dgisselq |
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| 270 |
75 |
dgisselq |
/*
|
| 271 |
96 |
dgisselq |
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x %s%s %2d %2d",
|
| 272 |
37 |
dgisselq |
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
|
| 273 |
|
|
// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
|
| 274 |
|
|
// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
|
| 275 |
4 |
dgisselq |
(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
|
| 276 |
75 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_halted)?"Z":"-",
|
| 277 |
4 |
dgisselq |
(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
|
| 278 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
|
| 279 |
75 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_valid)?"V":"-",
|
| 280 |
4 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-",
|
| 281 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-",
|
| 282 |
75 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?"D":"-",
|
| 283 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"d":"-",
|
| 284 |
4 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
|
| 285 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
|
| 286 |
96 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_alu)?"A":"-",
|
| 287 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_ce)?"a":"-",
|
| 288 |
75 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)?"M":"-",
|
| 289 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_ce)?"m":"-",
|
| 290 |
4 |
dgisselq |
(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
|
| 291 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-",
|
| 292 |
75 |
dgisselq |
(m_core->v__DOT__zippy__DOT__cmd_addr),
|
| 293 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ibus_err_flag)?"IB":" ",
|
| 294 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ubus_err_flag)?"UB":" ",
|
| 295 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__rdaddr,
|
| 296 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__wraddr);
|
| 297 |
4 |
dgisselq |
|
| 298 |
75 |
dgisselq |
printf(" PC0x%08x/%08x/%08x-%08x %s0x%08x",
|
| 299 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
| 300 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__ipc,
|
| 301 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__upc,
|
| 302 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
|
| 303 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":" ",
|
| 304 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc
|
| 305 |
|
|
);
|
| 306 |
96 |
dgisselq |
|
| 307 |
|
|
printf(" %s[%02x]=%08x(%08x)",
|
| 308 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce?"WR":"--",
|
| 309 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
|
| 310 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl,
|
| 311 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_spreg_vl);
|
| 312 |
75 |
dgisselq |
*/
|
| 313 |
96 |
dgisselq |
|
| 314 |
4 |
dgisselq |
|
| 315 |
96 |
dgisselq |
/*
|
| 316 |
|
|
printf(" SDSPI[%d,%d(%d),(%d)]",
|
| 317 |
75 |
dgisselq |
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy,
|
| 318 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
| 319 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_state,
|
| 320 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_rsp_state);
|
| 321 |
96 |
dgisselq |
printf(" LL[%d,%2x->CK=%d/%2x,%s,ST=%2d,TX=%2x,RX=%2x->%d,%2x] ",
|
| 322 |
75 |
dgisselq |
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_stb,
|
| 323 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_dat,
|
| 324 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_z_counter,
|
| 325 |
|
|
// (m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter==0)?1:0,
|
| 326 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter,
|
| 327 |
|
|
(m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_idle)?"IDLE":" ",
|
| 328 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_state,
|
| 329 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_byte,
|
| 330 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_ireg,
|
| 331 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_stb,
|
| 332 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_dat
|
| 333 |
|
|
);
|
| 334 |
96 |
dgisselq |
printf(" CRC=%02x/%2d",
|
| 335 |
75 |
dgisselq |
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc,
|
| 336 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc_cnt);
|
| 337 |
|
|
printf(" SPI(%d,%d,%d/%d,%d)->?",
|
| 338 |
|
|
m_core->o_sf_cs_n,
|
| 339 |
|
|
m_core->o_sd_cs_n,
|
| 340 |
|
|
m_core->o_spi_sck, m_core->v__DOT__sdcard_sck,
|
| 341 |
|
|
m_core->o_spi_mosi);
|
| 342 |
|
|
|
| 343 |
|
|
printf(" CK=%d,LN=%d",
|
| 344 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
| 345 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_lgblklen);
|
| 346 |
|
|
|
| 347 |
96 |
dgisselq |
|
| 348 |
75 |
dgisselq |
if (m_core->v__DOT__sdcard_controller__DOT__r_use_fifo){
|
| 349 |
|
|
printf(" FIFO");
|
| 350 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_fifo_wr)
|
| 351 |
96 |
dgisselq |
printf("-WR(%04x,%d,%d,%d)",
|
| 352 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_reg,
|
| 353 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_stb,
|
| 354 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_pkt_state,
|
| 355 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_have_data_response_token);
|
| 356 |
75 |
dgisselq |
else
|
| 357 |
96 |
dgisselq |
printf("-RD(%04x,%d,%d,%d)",
|
| 358 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_reg,
|
| 359 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_stb,
|
| 360 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_state,
|
| 361 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_complete
|
| 362 |
|
|
);
|
| 363 |
75 |
dgisselq |
}
|
| 364 |
|
|
|
| 365 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_rd)
|
| 366 |
|
|
printf(" LL-RD");
|
| 367 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr)
|
| 368 |
|
|
printf(" LL-WR");
|
| 369 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_have_start_token)
|
| 370 |
|
|
printf(" START-TOK");
|
| 371 |
96 |
dgisselq |
printf(" %3d/%02x",
|
| 372 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_addr,
|
| 373 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_byte&0x0ff);
|
| 374 |
|
|
*/
|
| 375 |
75 |
dgisselq |
|
| 376 |
96 |
dgisselq |
|
| 377 |
75 |
dgisselq |
/*
|
| 378 |
|
|
printf(" DMAC[%d]: %08x/%08x/%08x(%03x) -- (%d,%d,%c)%c%c:@%08x-[%4d,%4d/%4d,%4d-#%4d]%08x",
|
| 379 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state,
|
| 380 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_waddr,
|
| 381 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_raddr,
|
| 382 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_len,
|
| 383 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_blocklen_sub_one,
|
| 384 |
|
|
m_core->v__DOT__zippy__DOT__dc_cyc,
|
| 385 |
|
|
// m_core->v__DOT__zippy__DOT__dc_stb,
|
| 386 |
|
|
(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 2)?1:0,
|
| 387 |
|
|
|
| 388 |
|
|
((m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 4)
|
| 389 |
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 5)
|
| 390 |
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 6))?'W':'R',
|
| 391 |
|
|
//(m_core->v__DOT__zippy__DOT__dc_we)?'W':'R',
|
| 392 |
|
|
(m_core->v__DOT__zippy__DOT__dc_ack)?'A':' ',
|
| 393 |
|
|
(m_core->v__DOT__zippy__DOT__dc_stall)?'S':' ',
|
| 394 |
|
|
m_core->v__DOT__zippy__DOT__dc_addr,
|
| 395 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__rdaddr,
|
| 396 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nread,
|
| 397 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nracks,
|
| 398 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwacks,
|
| 399 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwritten,
|
| 400 |
|
|
m_core->v__DOT__zippy__DOT__dc_data);
|
| 401 |
|
|
|
| 402 |
|
|
printf(" %08x-PIC%08x",
|
| 403 |
|
|
m_core->v__DOT__zippy__DOT__main_int_vector,
|
| 404 |
|
|
m_core->v__DOT__zippy__DOT__pic_data);
|
| 405 |
|
|
*/
|
| 406 |
|
|
|
| 407 |
|
|
printf("\n"); fflush(stdout);
|
| 408 |
|
|
} m_last_writeout = writeout;
|
| 409 |
|
|
|
| 410 |
4 |
dgisselq |
}
|
| 411 |
|
|
|
| 412 |
|
|
};
|
| 413 |
|
|
|
| 414 |
|
|
BUSMASTER_TB *tb;
|
| 415 |
|
|
|
| 416 |
|
|
void busmaster_kill(int v) {
|
| 417 |
|
|
tb->kill();
|
| 418 |
75 |
dgisselq |
fprintf(stderr, "KILLED!!\n");
|
| 419 |
4 |
dgisselq |
exit(0);
|
| 420 |
|
|
}
|
| 421 |
|
|
|
| 422 |
|
|
int main(int argc, char **argv) {
|
| 423 |
|
|
Verilated::commandArgs(argc, argv);
|
| 424 |
|
|
tb = new BUSMASTER_TB;
|
| 425 |
|
|
|
| 426 |
|
|
// signal(SIGINT, busmaster_kill);
|
| 427 |
|
|
|
| 428 |
|
|
tb->reset();
|
| 429 |
96 |
dgisselq |
if (argc > 1)
|
| 430 |
|
|
tb->setsdcard(argv[1]);
|
| 431 |
|
|
else
|
| 432 |
|
|
tb->setsdcard("/dev/zero");
|
| 433 |
4 |
dgisselq |
|
| 434 |
|
|
while(1)
|
| 435 |
|
|
tb->tick();
|
| 436 |
|
|
|
| 437 |
|
|
exit(0);
|
| 438 |
|
|
}
|
| 439 |
|
|
|
