Subversion Repositories xulalx25soc

////////////////////////////////////////////////////////////////////////////////

//

// Filename:    busmaster_tb.cpp

//

// Project:     FPGA library development (XuLA2 development board)

//

// Purpose:     This is piped version of the testbench for the busmaster

//              verilog code.  The busmaster code is designed to be a complete

//      code set implementing all of the functionality of the XESS XuLA2

//      development board.  If done well, the programs talking to this one

//      should be able to talk to the board and apply the same tests to the

//      board itself.

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015-2016, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory, run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

#include <signal.h>

#include <time.h>

#include <ctype.h>

#include "verilated.h"

#include "Vbusmaster.h"

#include "testb.h"

// #include "twoc.h"

#include "pipecmdr.h"

#include "qspiflashsim.h"

#include "sdramsim.h"

#include "sdspisim.h"

#include "uartsim.h"

#include "port.h"

// Add a reset line, since Vbusmaster doesn't have one

class   Vbusmasterr : public Vbusmaster {

public:

        int     i_rst;

        virtual ~Vbusmasterr() {}

};

// No particular "parameters" need definition or redefinition here.

class   BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {

public:

        unsigned long   m_tx_busy_count;

        QSPIFLASHSIM    m_flash;

        SDSPISIM        m_sdcard;

        SDRAMSIM        m_sdram;

        unsigned        m_last_led;

        time_t          m_start_time;

        bool            m_last_writeout;

        UARTSIM         m_uart;

        BUSMASTER_TB(void) : PIPECMDR(FPGAPORT), m_uart(FPGAPORT+1) {

                m_start_time = time(NULL);

        }

        void    reset(void) {

                m_core->i_clk = 1;

                m_core->eval();

        }

        void    setsdcard(const char *fn) {

                m_sdcard.load(fn);

                printf("LOADING SDCARD FROM: \'%s\'\n", fn);

        }

        void    tick(void) {

                int     flash_miso, sdcard_miso;

                if ((m_tickcount & ((1<<28)-1))==0) {

                        double  ticks_per_second = m_tickcount;

                        time_t  seconds_passed = time(NULL)-m_start_time;

                        if (seconds_passed != 0) {

                        ticks_per_second /= (double)(time(NULL) - m_start_time);

                        printf(" ********   %.6f TICKS PER SECOND\n",

                                ticks_per_second);

                        }

                }

                // Set up the bus before any clock tick

                m_core->i_clk = 1;

                flash_miso = (m_flash(m_core->o_sf_cs_n,

                                        m_core->o_spi_sck,

                                        m_core->o_spi_mosi)&0x02)?1:0;

                sdcard_miso = m_sdcard(m_core->o_sd_cs_n, m_core->o_spi_sck,

                                        m_core->o_spi_mosi);

                if ((m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))

                        m_core->i_spi_miso = 1;

                else if ((!m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))

                        m_core->i_spi_miso = flash_miso;

                else if ((m_core->o_sf_cs_n)&&(!m_core->o_sd_cs_n))

                        m_core->i_spi_miso = sdcard_miso;

                else

                        assert((m_core->o_sf_cs_n)||(m_core->o_sd_cs_n));

                m_core->i_ram_data = m_sdram(1,

                                m_core->o_ram_cke, m_core->o_ram_cs_n,

                                m_core->o_ram_ras_n, m_core->o_ram_cas_n,

                                m_core->o_ram_we_n, m_core->o_ram_bs,

                                m_core->o_ram_addr, m_core->o_ram_drive_data,

                                m_core->o_ram_data);

                m_core->i_rx_uart = m_uart(m_core->o_tx_uart,

                                m_core->v__DOT__serialport__DOT__r_setup);

                PIPECMDR::tick();

                bool    writeout = false;

                if ((writeout)||(m_last_writeout)) {

                        printf("%08lx:", m_tickcount);

                        printf("\n"); fflush(stdout);

                } m_last_writeout = writeout;

        }

};

BUSMASTER_TB    *tb;

void    busmaster_kill(int v) {

        tb->kill();

        fprintf(stderr, "KILLED!!\n");

        exit(0);

}

int     main(int argc, char **argv) {

        Verilated::commandArgs(argc, argv);

        tb = new BUSMASTER_TB;

        // signal(SIGINT,  busmaster_kill);

        tb->reset();

        if (argc > 1)

                tb->setsdcard(argv[1]);

        else

                tb->setsdcard("/dev/zero");

        while(1)

                tb->tick();

        exit(0);

}