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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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// Filename: busmaster_tb.cpp
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//
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// Project: FPGA library development (XuLA2 development board)
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//
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// Purpose: This is piped version of the testbench for the busmaster
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// verilog code. The busmaster code is designed to be a complete
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dgisselq |
// code set implementing all of the functionality of the XESS XuLA2
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// development board. If done well, the programs talking to this one
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// should be able to talk to the board and apply the same tests to the
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// board itself.
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dgisselq |
//
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dgisselq |
// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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dgisselq |
//
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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <signal.h>
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#include <time.h>
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#include <ctype.h>
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#include "verilated.h"
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#include "Vbusmaster.h"
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#include "testb.h"
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// #include "twoc.h"
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#include "pipecmdr.h"
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#include "qspiflashsim.h"
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#include "sdramsim.h"
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#include "sdspisim.h"
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#include "uartsim.h"
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#include "port.h"
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// Add a reset line, since Vbusmaster doesn't have one
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class Vbusmasterr : public Vbusmaster {
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public:
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int i_rst;
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virtual ~Vbusmasterr() {}
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};
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// No particular "parameters" need definition or redefinition here.
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class BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {
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public:
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unsigned long m_tx_busy_count;
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QSPIFLASHSIM m_flash;
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SDSPISIM m_sdcard;
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SDRAMSIM m_sdram;
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unsigned m_last_led, m_last_pic, m_last_tx_state;
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time_t m_start_time;
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bool m_last_writeout;
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UARTSIM m_uart;
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int m_last_bus_owner, m_busy;
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BUSMASTER_TB(void) : PIPECMDR(FPGAPORT), m_uart(FPGAPORT+1) {
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m_start_time = time(NULL);
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m_last_pic = 0;
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m_last_tx_state = 0;
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}
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void reset(void) {
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m_core->i_clk = 1;
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m_core->eval();
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}
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void setsdcard(const char *fn) {
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m_sdcard.load(fn);
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printf("LOADING SDCARD FROM: \'%s\'\n", fn);
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}
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void tick(void) {
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int flash_miso, sdcard_miso;
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if ((m_tickcount & ((1<<28)-1))==0) {
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double ticks_per_second = m_tickcount;
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time_t seconds_passed = time(NULL)-m_start_time;
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if (seconds_passed != 0) {
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ticks_per_second /= (double)(time(NULL) - m_start_time);
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printf(" ******** %.6f TICKS PER SECOND\n",
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ticks_per_second);
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}
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}
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// Set up the bus before any clock tick
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m_core->i_clk = 1;
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flash_miso = (m_flash(m_core->o_sf_cs_n,
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m_core->o_spi_sck,
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m_core->o_spi_mosi)&0x02)?1:0;
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sdcard_miso = m_sdcard(m_core->o_sd_cs_n, m_core->o_spi_sck,
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m_core->o_spi_mosi);
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if ((m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))
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m_core->i_spi_miso = 1;
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else if ((!m_core->o_sf_cs_n)&&(m_core->o_sd_cs_n))
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m_core->i_spi_miso = flash_miso;
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else if ((m_core->o_sf_cs_n)&&(!m_core->o_sd_cs_n))
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m_core->i_spi_miso = sdcard_miso;
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else
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assert((m_core->o_sf_cs_n)||(m_core->o_sd_cs_n));
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m_core->i_ram_data = m_sdram(1,
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m_core->o_ram_cke, m_core->o_ram_cs_n,
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m_core->o_ram_ras_n, m_core->o_ram_cas_n,
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m_core->o_ram_we_n, m_core->o_ram_bs,
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m_core->o_ram_addr, m_core->o_ram_drive_data,
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m_core->o_ram_data);
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m_core->i_rx_uart = m_uart(m_core->o_tx_uart,
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m_core->v__DOT__serialport__DOT__r_setup);
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PIPECMDR::tick();
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// #define DEBUGGING_OUTPUT
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#define XULA25
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#ifdef DEBUGGING_OUTPUT
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bool writeout = false;
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/*
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if (m_core->v__DOT__sdram__DOT__r_pending)
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writeout = true;
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else if (m_core->v__DOT__sdram__DOT__bank_active[0])
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writeout = true;
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else if (m_core->v__DOT__sdram__DOT__bank_active[1])
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writeout = true;
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else if (m_core->v__DOT__sdram__DOT__bank_active[2])
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writeout = true;
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else if (m_core->v__DOT__sdram__DOT__bank_active[3])
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writeout = true;
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*/
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if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
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writeout = true;
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/*
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if ((m_core->v__DOT__wbu_cyc)&&(!m_core->v__DOT__wbu_we))
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writeout = true;
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if (m_core->v__DOT__genbus__DOT__exec_stb)
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writeout = true;
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*/
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if ((m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
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&&(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction == 0x7883ffff))
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m_busy+=2;
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else if (m_busy > 0) m_busy--;
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#define v__DOT__wb_addr v__DOT__dwb_addr
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#define v__DOT__dwb_stall v__DOT__wb_stall
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#define v__DOT__dwb_ack v__DOT__wb_ack
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#define v__DOT__wb_cyc v__DOT__dwb_cyc
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#define v__DOT__wb_stb v__DOT__dwb_stb
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#define v__DOT__wb_we v__DOT__dwb_we
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#define v__DOT__dwb_idata v__DOT__wb_idata
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#define v__DOT__wb_data v__DOT__dwb_odata
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if ((!m_core->v__DOT__zippy__DOT__cmd_halt)
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&&(!m_core->v__DOT__zippy__DOT__thecpu__DOT__sleep))
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writeout = true;
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// if (m_core->v__DOT__uart_tx_int)
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// writeout = true;
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#ifdef XULA25
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if (m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_any)
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writeout = true;
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#endif
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#ifdef XULA25
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unsigned this_pic = ((m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_enable)<<16) |
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(m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_state);
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#else
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unsigned this_pic = 0;
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#endif
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// if (this_pic != m_last_pic)
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// writeout = true;
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unsigned tx_state = ((m_core->v__DOT__serialport__DOT__txmod__DOT__zero_baud_counter)<<20)
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|((m_core->v__DOT__serialport__DOT__txmod__DOT__r_busy)<<16)
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|((m_core->v__DOT__serialport__DOT__txmod__DOT__lcl_data)<<8)
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|((m_core->v__DOT__serialport__DOT__txmod__DOT__baud_counter&0x0f)<<4)
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|(m_core->v__DOT__serialport__DOT__txmod__DOT__state);
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if (tx_state != m_last_tx_state)
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writeout = true;
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int bus_owner = m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner;
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bus_owner |= (m_core->v__DOT__wbu_cyc)?2:0;
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bus_owner |= (m_core->v__DOT__dwb_cyc)?4:0;
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bus_owner |= (m_core->v__DOT__wb_cyc)?8:0;
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bus_owner |= (m_core->v__DOT__wb_cyc)?16:0;
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bus_owner |= (m_core->v__DOT__wbu_stb)?32:0;
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bus_owner |= (m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl)?64:0;
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bus_owner |= (m_core->v__DOT__wb_stb)?128:0;
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bus_owner |= (m_core->v__DOT____Vcellinp__wbu_zip_arbiter____pinNumber10)?256:0;
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#ifdef XULA25
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bus_owner |= (m_core->v__DOT__zippy__DOT__ext_cyc)?512:0;
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#endif
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if (bus_owner != m_last_bus_owner)
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| 216 |
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writeout = true;
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/*
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| 218 |
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writeout = (writeout)||(m_core->i_rx_stb)
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| 219 |
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||((m_core->o_tx_stb)&&(!m_core->i_tx_busy));
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| 220 |
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writeout = (writeout)||(m_core->v__DOT____Vcellinp__genbus____pinNumber9);
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| 221 |
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writeout = (writeout)||(m_core->v__DOT__wb_stb);
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| 222 |
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writeout = (writeout)||(m_core->v__DOT__wb_err);
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| 223 |
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*/
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| 224 |
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dgisselq |
if ((writeout)||(m_last_writeout)) {
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| 226 |
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dgisselq |
m_last_bus_owner = bus_owner;
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| 227 |
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m_last_pic = this_pic;
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| 228 |
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m_last_tx_state = tx_state;
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| 229 |
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dgisselq |
printf("%08lx:", m_tickcount);
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| 230 |
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| 231 |
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dgisselq |
/*
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| 232 |
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printf("%d/%02x %d/%02x%s ",
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| 233 |
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m_core->i_rx_stb, m_core->i_rx_data,
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| 234 |
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m_core->o_tx_stb, m_core->o_tx_data,
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| 235 |
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m_core->i_tx_busy?"/BSY":" ");
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| 236 |
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*/
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| 237 |
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| 238 |
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printf("(%d/%d,%d/%d->%d),(%c:%d,%d->%d)|%c[%08x/%08x]@%08x %c%c%c",
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| 239 |
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m_core->v__DOT__wbu_cyc,
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| 240 |
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m_core->v__DOT____Vcellinp__wbu_zip_arbiter____pinNumber10,
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| 241 |
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m_core->v__DOT__dwb_cyc, // was zip_cyc
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| 242 |
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#ifdef XULA25
|
| 243 |
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(m_core->v__DOT__zippy__DOT__ext_cyc),
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| 244 |
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#else
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| 245 |
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0,
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| 246 |
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#endif
|
| 247 |
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m_core->v__DOT__wb_cyc,
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| 248 |
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//
|
| 249 |
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m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner?'Z':'j',
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| 250 |
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m_core->v__DOT__wbu_stb,
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| 251 |
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// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
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| 252 |
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m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
|
| 253 |
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m_core->v__DOT__wb_stb,
|
| 254 |
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//
|
| 255 |
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(m_core->v__DOT__wb_we)?'W':'R',
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| 256 |
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m_core->v__DOT__wb_data,
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| 257 |
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m_core->v__DOT__dwb_idata,
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| 258 |
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m_core->v__DOT__wb_addr,
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| 259 |
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(m_core->v__DOT__dwb_ack)?'A':
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| 260 |
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(m_core->v__DOT____Vcellinp__genbus____pinNumber9)?'a':' ',
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| 261 |
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(m_core->v__DOT__dwb_stall)?'S':
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| 262 |
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(m_core->v__DOT____Vcellinp__genbus____pinNumber10)?'s':' ',
|
| 263 |
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(m_core->v__DOT__wb_err)?'E':'.');
|
| 264 |
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| 265 |
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/*
|
| 266 |
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// UART-Wishbone bus converter debug lines
|
| 267 |
|
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printf(" RUNWB %d:%09lx %d@0x%08x %3x %3x %d %d/%d/%d %d:%09lx",
|
| 268 |
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m_core->v__DOT__genbus__DOT__fifo_in_stb,
|
| 269 |
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m_core->v__DOT__genbus__DOT__fifo_in_word,
|
| 270 |
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m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
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| 271 |
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m_core->v__DOT__wbu_addr,
|
| 272 |
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m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
|
| 273 |
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m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed,
|
| 274 |
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m_core->v__DOT__genbus__DOT__runwb__DOT__w_eow,
|
| 275 |
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m_core->v__DOT__genbus__DOT__runwb__DOT__last_read_request,
|
| 276 |
|
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m_core->v__DOT__genbus__DOT__runwb__DOT__last_ack,
|
| 277 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__zero_acks,
|
| 278 |
|
|
m_core->v__DOT__genbus__DOT__exec_stb,
|
| 279 |
|
|
m_core->v__DOT__genbus__DOT__exec_word);
|
| 280 |
|
|
*/
|
| 281 |
|
|
|
| 282 |
|
|
/*
|
| 283 |
|
|
// UART-Wishbone bus converter debug lines
|
| 284 |
|
|
printf(" WBU[%d,%3d,%3d]",
|
| 285 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__wb_state,
|
| 286 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_len,
|
| 287 |
|
|
m_core->v__DOT__genbus__DOT__runwb__DOT__r_acks_needed);
|
| 288 |
|
|
*/
|
| 289 |
|
|
|
| 290 |
|
|
/*
|
| 291 |
|
|
// SDRAM debug lines
|
| 292 |
|
|
printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
|
| 293 |
|
|
(m_core->v__DOT__sdram_sel)?'!':' ',
|
| 294 |
|
|
m_core->o_ram_cs_n, m_core->o_ram_ras_n,
|
| 295 |
|
|
m_core->o_ram_cas_n, m_core->o_ram_we_n,
|
| 296 |
|
|
m_core->o_ram_bs, m_core->o_ram_data,
|
| 297 |
|
|
(m_core->o_ram_drive_data)?'D':'-',
|
| 298 |
|
|
m_core->o_ram_addr,
|
| 299 |
|
|
(m_core->o_ram_addr>>10)&1,
|
| 300 |
|
|
m_core->i_ram_data,
|
| 301 |
|
|
(m_core->o_ram_drive_data)?'-':'V');
|
| 302 |
|
|
|
| 303 |
|
|
printf(" SD[%d,%d-%3x%d]",
|
| 304 |
|
|
m_core->v__DOT__sdram__DOT__r_state,
|
| 305 |
|
|
m_sdram.pwrup(),
|
| 306 |
|
|
m_core->v__DOT__sdram__DOT__refresh_clk,
|
| 307 |
|
|
m_core->v__DOT__sdram__DOT__need_refresh);
|
| 308 |
|
|
|
| 309 |
|
|
printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
|
| 310 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[0],
|
| 311 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[0],
|
| 312 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[1],
|
| 313 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[1],
|
| 314 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[2],
|
| 315 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[2],
|
| 316 |
|
|
m_core->v__DOT__sdram__DOT__bank_active[3],
|
| 317 |
|
|
m_core->v__DOT__sdram__DOT__bank_row[3],
|
| 318 |
|
|
m_core->v__DOT__sdram__DOT__clocks_til_idle,
|
| 319 |
|
|
m_core->v__DOT__sdram__DOT__r_barrell_ack);
|
| 320 |
|
|
|
| 321 |
|
|
printf(" %s%s%c[%08x@%06x]",
|
| 322 |
|
|
(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
|
| 323 |
|
|
(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
|
| 324 |
|
|
(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
|
| 325 |
|
|
(m_core->v__DOT__sdram__DOT__r_we)
|
| 326 |
|
|
?(m_core->v__DOT__sdram__DOT__r_data)
|
| 327 |
|
|
:(m_core->v__DOT__sdram_data),
|
| 328 |
|
|
(m_core->v__DOT__sdram__DOT__r_addr));
|
| 329 |
|
|
*/
|
| 330 |
|
|
|
| 331 |
|
|
// CPU Pipeline debugging
|
| 332 |
|
|
printf("%s%s%s%s%s%s%s%s%s%s%s",
|
| 333 |
|
|
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
|
| 334 |
|
|
// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
|
| 335 |
|
|
// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
|
| 336 |
|
|
(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
|
| 337 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_halted)?"Z":"-",
|
| 338 |
|
|
(m_core->v__DOT__zippy__DOT__cpu_break)?"!":"-",
|
| 339 |
|
|
(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
|
| 340 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__gie)?"G":"-",
|
| 341 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
|
| 342 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_valid)?"V":"-",
|
| 343 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_illegal)?"i":" ",
|
| 344 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
|
| 345 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"G":"-",
|
| 346 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"L":"-");
|
| 347 |
|
|
printf("|%s%s%s%s%s%s",
|
| 348 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?"D":"-",
|
| 349 |
|
|
(dcd_ce())?"d":"-",
|
| 350 |
|
|
"x", // (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdA_stall)?"A":"-",
|
| 351 |
|
|
"x", // (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdB_stall)?"B":"-",
|
| 352 |
|
|
"x", // (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdF_stall)?"F":"-",
|
| 353 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_illegal)?"i":"-");
|
| 354 |
|
|
|
| 355 |
|
|
printf("|%s%s%s%s%s%s%s%s%s%s",
|
| 356 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
|
| 357 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
|
| 358 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_stall)?"s":"-",
|
| 359 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_illegal)?"i":"-",
|
| 360 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_break)?"B":"-",
|
| 361 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__genblk5__DOT__r_op_lock)?"L":"-",
|
| 362 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_op_pipe)?"P":"-",
|
| 363 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__break_pending)?"p":"-",
|
| 364 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_gie)?"G":"-",
|
| 365 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_alu)?"A":"-");
|
| 366 |
|
|
printf("|%s%s%s%s%s",
|
| 367 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_ce)?"a":"-",
|
| 368 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_stall)?"s":"-",
|
| 369 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__doalu__DOT__genblk2__DOT__r_busy)?"B":"-",
|
| 370 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_gie)?"G":"-",
|
| 371 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_alu_illegal)?"i":"-");
|
| 372 |
|
|
printf("|%s%s%s%2x %s%s%s %2d %2d",
|
| 373 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)?"M":"-",
|
| 374 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_ce)?"m":"-",
|
| 375 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__adf_ce_unconditional)?"!":"-",
|
| 376 |
|
|
(m_core->v__DOT__zippy__DOT__cmd_addr),
|
| 377 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__bus_err)?"BE":" ",
|
| 378 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ibus_err_flag)?"IB":" ",
|
| 379 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ubus_err_flag)?"UB":" ",
|
| 380 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__rdaddr,
|
| 381 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__wraddr);
|
| 382 |
|
|
#ifdef XULA25
|
| 383 |
|
|
printf("|%s%s",
|
| 384 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__div_busy)?"D":"-",
|
| 385 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__div_error)?"E":"-");
|
| 386 |
|
|
#endif
|
| 387 |
|
|
printf("|%s%s[%2x]%08x",
|
| 388 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce)?"W":"-",
|
| 389 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_flags_ce)?"F":"-",
|
| 390 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
|
| 391 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl);
|
| 392 |
|
|
|
| 393 |
|
|
// Program counter debugging
|
| 394 |
|
|
printf(" PC0x%08x/%08x/%08x-%08x %s0x%08x",
|
| 395 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
| 396 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__ipc,
|
| 397 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__upc,
|
| 398 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
|
| 399 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":" ",
|
| 400 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc
|
| 401 |
|
|
);
|
| 402 |
|
|
// More in-depth
|
| 403 |
|
|
printf("[%c%08x,%c%08x,%c%08x]",
|
| 404 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)?'D':'-',
|
| 405 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_pc,
|
| 406 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?'O':'-',
|
| 407 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__op_pc,
|
| 408 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_valid)?'A':'-',
|
| 409 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_pc);
|
| 410 |
|
|
|
| 411 |
|
|
#ifdef XULA25
|
| 412 |
|
|
// Prefetch debugging
|
| 413 |
|
|
printf(" [PC%08x,LST%08x]->[%d%s%s](%d,%08x/%08x)->%08x@%08x",
|
| 414 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
| 415 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__lastpc,
|
| 416 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__rvsrc,
|
| 417 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__rvsrc)
|
| 418 |
|
|
?((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_pc)?"P":" ")
|
| 419 |
|
|
:((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_pc)?"p":" "),
|
| 420 |
|
|
(!m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__rvsrc)
|
| 421 |
|
|
?((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_last)?"l":" ")
|
| 422 |
|
|
:((m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_v_from_last)?"L":" "),
|
| 423 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__isrc,
|
| 424 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_pc_cache,
|
| 425 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_last_cache,
|
| 426 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction,
|
| 427 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__instruction_pc);
|
| 428 |
|
|
#else
|
| 429 |
|
|
printf(" [PC%08x,R%08x]%s%s%s",
|
| 430 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_pc,
|
| 431 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__r_addr,
|
| 432 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__w_pc_out_of_bounds)?"OOB":" ",
|
| 433 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__w_running_out_of_cache)?"RUN":" ",
|
| 434 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf__DOT__w_ran_off_end_of_cache)?"END":" ");
|
| 435 |
|
|
#endif
|
| 436 |
|
|
|
| 437 |
|
|
// Decode Stage debugging
|
| 438 |
|
|
// (nothing)
|
| 439 |
|
|
|
| 440 |
|
|
// Op Stage debugging
|
| 441 |
|
|
printf(" Op(%02x,%02x->%02x)",
|
| 442 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__dcdOp,
|
| 443 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__opn,
|
| 444 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__opR);
|
| 445 |
|
|
|
| 446 |
|
|
printf(" %s[%02x]=%08x(%08x)",
|
| 447 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_ce?"WR":"--",
|
| 448 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_reg_id,
|
| 449 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_gpreg_vl,
|
| 450 |
|
|
#ifdef XULA25
|
| 451 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__wr_spreg_vl
|
| 452 |
|
|
#else
|
| 453 |
|
|
|
| 454 |
|
|
#endif
|
| 455 |
|
|
);
|
| 456 |
|
|
printf(" Rid=(%d|%d)?%02x:%02x",
|
| 457 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_wr,
|
| 458 |
|
|
#ifdef XULA25
|
| 459 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__div_valid,
|
| 460 |
|
|
#else
|
| 461 |
|
|
0,
|
| 462 |
|
|
#endif
|
| 463 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__alu_reg,
|
| 464 |
|
|
m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_wreg);
|
| 465 |
|
|
|
| 466 |
|
|
// domem, the pipelined memory unit debugging
|
| 467 |
|
|
printf(" M[%s@0x%08x]",
|
| 468 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid_mem)
|
| 469 |
|
|
?((m_core->v__DOT__zippy__DOT__thecpu__DOT__opn&1)?"W":"R")
|
| 470 |
|
|
:"-",
|
| 471 |
|
|
#ifdef XULA25
|
| 472 |
|
|
m_core->v__DOT__zippy__DOT__cpu_addr
|
| 473 |
|
|
#else
|
| 474 |
|
|
|
| 475 |
|
|
#endif
|
| 476 |
|
|
);
|
| 477 |
|
|
printf("%s%s",
|
| 478 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__domem__DOT__cyc)?"B":"-",
|
| 479 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_rdbusy)?"r":"-");
|
| 480 |
|
|
/*
|
| 481 |
|
|
printf(" %s-%s %04x/%04x",
|
| 482 |
|
|
(m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_any)?"PIC":"pic",
|
| 483 |
|
|
(m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_gie)?"INT":"( )",
|
| 484 |
|
|
m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_enable,
|
| 485 |
|
|
m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_int_state);
|
| 486 |
|
|
*/
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
printf(" %s",
|
| 490 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__cc_invalid_for_dcd)?"CCI":" ");
|
| 491 |
|
|
/*
|
| 492 |
|
|
// Illegal instruction debugging
|
| 493 |
|
|
printf(" ILL[%s%s%s%s%s%s]",
|
| 494 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_err)?"WB":" ",
|
| 495 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_illegal)?"PF":" ",
|
| 496 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_illegal)?"DCD":" ",
|
| 497 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_illegal)?"OP":" ",
|
| 498 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__r_alu_illegal)?"ALU":" ",
|
| 499 |
|
|
(m_core->v__DOT__zippy__DOT__thecpu__DOT__ill_err_u)?"ILL":" ");
|
| 500 |
|
|
|
| 501 |
|
|
*/
|
| 502 |
|
|
|
| 503 |
|
|
/*
|
| 504 |
|
|
printf(" UART%08x/%d-%08x", m_last_tx_state,
|
| 505 |
|
|
m_core->v__DOT__serialport__DOT__txmod__DOT__zero_baud_counter,
|
| 506 |
|
|
m_core->v__DOT__serialport__DOT__txmod__DOT__baud_counter);
|
| 507 |
|
|
*/
|
| 508 |
|
|
|
| 509 |
|
|
// Debug some conditions
|
| 510 |
|
|
if (m_core->v__DOT__zippy__DOT__thecpu__DOT__ubreak)
|
| 511 |
|
|
printf(" BREAK");
|
| 512 |
|
|
// if (m_core->v__DOT__zippy__DOT__thecpu__DOT__w_switch_to_interrupt)
|
| 513 |
|
|
// printf(" TO-INT");
|
| 514 |
|
|
#ifdef XULA25
|
| 515 |
|
|
if (m_core->v__DOT__zippy__DOT__genblk10__DOT__pic__DOT__r_interrupt)
|
| 516 |
|
|
printf(" INTERRUPT");
|
| 517 |
|
|
#endif
|
| 518 |
|
|
|
| 519 |
|
|
/*
|
| 520 |
|
|
printf(" SDSPI[%d,%d(%d),(%d)]",
|
| 521 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy,
|
| 522 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
| 523 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_state,
|
| 524 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_rsp_state);
|
| 525 |
|
|
printf(" LL[%d,%2x->CK=%d/%2x,%s,ST=%2d,TX=%2x,RX=%2x->%d,%2x] ",
|
| 526 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_stb,
|
| 527 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_dat,
|
| 528 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_z_counter,
|
| 529 |
|
|
// (m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter==0)?1:0,
|
| 530 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter,
|
| 531 |
|
|
(m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_idle)?"IDLE":" ",
|
| 532 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_state,
|
| 533 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_byte,
|
| 534 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_ireg,
|
| 535 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_stb,
|
| 536 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_dat
|
| 537 |
|
|
);
|
| 538 |
|
|
printf(" CRC=%02x/%2d",
|
| 539 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc,
|
| 540 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc_cnt);
|
| 541 |
|
|
printf(" SPI(%d,%d,%d/%d,%d)->?",
|
| 542 |
|
|
m_core->o_sf_cs_n,
|
| 543 |
|
|
m_core->o_sd_cs_n,
|
| 544 |
|
|
m_core->o_spi_sck, m_core->v__DOT__sdcard_sck,
|
| 545 |
|
|
m_core->o_spi_mosi);
|
| 546 |
|
|
|
| 547 |
|
|
printf(" CK=%d,LN=%d",
|
| 548 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
| 549 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_lgblklen);
|
| 550 |
|
|
|
| 551 |
|
|
|
| 552 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_use_fifo){
|
| 553 |
|
|
printf(" FIFO");
|
| 554 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_fifo_wr)
|
| 555 |
|
|
printf("-WR(%04x,%d,%d,%d)",
|
| 556 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_reg,
|
| 557 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_stb,
|
| 558 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_pkt_state,
|
| 559 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_have_data_response_token);
|
| 560 |
|
|
else
|
| 561 |
|
|
printf("-RD(%04x,%d,%d,%d)",
|
| 562 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_reg,
|
| 563 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_stb,
|
| 564 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_state,
|
| 565 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_complete
|
| 566 |
|
|
);
|
| 567 |
|
|
}
|
| 568 |
|
|
|
| 569 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_rd)
|
| 570 |
|
|
printf(" LL-RD");
|
| 571 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr)
|
| 572 |
|
|
printf(" LL-WR");
|
| 573 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_have_start_token)
|
| 574 |
|
|
printf(" START-TOK");
|
| 575 |
|
|
printf(" %3d/%02x",
|
| 576 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_addr,
|
| 577 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_byte&0x0ff);
|
| 578 |
|
|
*/
|
| 579 |
|
|
|
| 580 |
|
|
|
| 581 |
|
|
/*
|
| 582 |
|
|
printf(" DMAC[%d]: %08x/%08x/%08x(%03x) -- (%d,%d,%c)%c%c:@%08x-[%4d,%4d/%4d,%4d-#%4d]%08x",
|
| 583 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state,
|
| 584 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_waddr,
|
| 585 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_raddr,
|
| 586 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_len,
|
| 587 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__cfg_blocklen_sub_one,
|
| 588 |
|
|
m_core->v__DOT__zippy__DOT__dc_cyc,
|
| 589 |
|
|
// m_core->v__DOT__zippy__DOT__dc_stb,
|
| 590 |
|
|
(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 2)?1:0,
|
| 591 |
|
|
|
| 592 |
|
|
((m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 4)
|
| 593 |
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 5)
|
| 594 |
|
|
||(m_core->v__DOT__zippy__DOT__dma_controller__DOT__dma_state == 6))?'W':'R',
|
| 595 |
|
|
//(m_core->v__DOT__zippy__DOT__dc_we)?'W':'R',
|
| 596 |
|
|
(m_core->v__DOT__zippy__DOT__dc_ack)?'A':' ',
|
| 597 |
|
|
(m_core->v__DOT__zippy__DOT__dc_stall)?'S':' ',
|
| 598 |
|
|
m_core->v__DOT__zippy__DOT__dc_addr,
|
| 599 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__rdaddr,
|
| 600 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nread,
|
| 601 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nracks,
|
| 602 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwacks,
|
| 603 |
|
|
m_core->v__DOT__zippy__DOT__dma_controller__DOT__nwritten,
|
| 604 |
|
|
m_core->v__DOT__zippy__DOT__dc_data);
|
| 605 |
|
|
|
| 606 |
|
|
printf(" %08x-PIC%08x",
|
| 607 |
|
|
m_core->v__DOT__zippy__DOT__main_int_vector,
|
| 608 |
|
|
m_core->v__DOT__zippy__DOT__pic_data);
|
| 609 |
|
|
*/
|
| 610 |
|
|
|
| 611 |
75 |
dgisselq |
printf("\n"); fflush(stdout);
|
| 612 |
|
|
} m_last_writeout = writeout;
|
| 613 |
113 |
dgisselq |
|
| 614 |
|
|
int writing_to_uart;
|
| 615 |
|
|
writing_to_uart = (m_core->v__DOT__wb_stb)
|
| 616 |
|
|
&&(m_core->v__DOT__wb_addr == 0x010b)
|
| 617 |
|
|
&&(m_core->v__DOT__wb_we);
|
| 618 |
|
|
if (writing_to_uart) {
|
| 619 |
|
|
printf("SENT-TO-UART: %02x %c\n",
|
| 620 |
|
|
(m_core->v__DOT__wb_data & 0x0ff),
|
| 621 |
|
|
isgraph(m_core->v__DOT__wb_data&0x0ff)
|
| 622 |
|
|
? m_core->v__DOT__wb_data&0x0ff
|
| 623 |
|
|
: '.');
|
| 624 |
|
|
assert((m_core->v__DOT__wb_data & (~0xff))==0);
|
| 625 |
|
|
}
|
| 626 |
|
|
#endif // DEBUGGING_OUTPUT
|
| 627 |
4 |
dgisselq |
}
|
| 628 |
|
|
|
| 629 |
113 |
dgisselq |
bool dcd_ce(void) {
|
| 630 |
|
|
if (!m_core->v__DOT__zippy__DOT__thecpu__DOT__r_dcdvalid)
|
| 631 |
|
|
return true;
|
| 632 |
|
|
if (!m_core->v__DOT__zippy__DOT__thecpu__DOT__op_stall)
|
| 633 |
|
|
return true;
|
| 634 |
|
|
return false;
|
| 635 |
|
|
}
|
| 636 |
|
|
|
| 637 |
4 |
dgisselq |
};
|
| 638 |
|
|
|
| 639 |
|
|
BUSMASTER_TB *tb;
|
| 640 |
|
|
|
| 641 |
|
|
void busmaster_kill(int v) {
|
| 642 |
|
|
tb->kill();
|
| 643 |
75 |
dgisselq |
fprintf(stderr, "KILLED!!\n");
|
| 644 |
4 |
dgisselq |
exit(0);
|
| 645 |
|
|
}
|
| 646 |
|
|
|
| 647 |
|
|
int main(int argc, char **argv) {
|
| 648 |
|
|
Verilated::commandArgs(argc, argv);
|
| 649 |
|
|
tb = new BUSMASTER_TB;
|
| 650 |
|
|
|
| 651 |
|
|
// signal(SIGINT, busmaster_kill);
|
| 652 |
|
|
|
| 653 |
|
|
tb->reset();
|
| 654 |
96 |
dgisselq |
if (argc > 1)
|
| 655 |
|
|
tb->setsdcard(argv[1]);
|
| 656 |
|
|
else
|
| 657 |
|
|
tb->setsdcard("/dev/zero");
|
| 658 |
4 |
dgisselq |
|
| 659 |
|
|
while(1)
|
| 660 |
|
|
tb->tick();
|
| 661 |
|
|
|
| 662 |
|
|
exit(0);
|
| 663 |
|
|
}
|
| 664 |
|
|
|
