Subversion Repositories xulalx25soc

//

//

// Filename:    busmaster_tb.cpp

//

// Project:     FPGA library development (XuLA2 development board)

//

// Purpose:     This is piped version of the testbench for the busmaster

//              verilog code.  The busmaster code is designed to be a complete

//              code set implementing all of the functionality of the XESS

//              XuLA2 development board.  If done well, the programs talking to

//              this one should be able to talk to the board and apply the

//              same tests to the board itself.

//

// Creator:     Dan Gisselquist

//              Gisselquist Tecnology, LLC

//

// Copyright:   2015

//

//

#include <signal.h>

#include <time.h>

#include "verilated.h"

#include "Vbusmaster.h"

#include "testb.h"

// #include "twoc.h"

#include "pipecmdr.h"

#include "qspiflashsim.h"

#include "sdramsim.h"

#include "port.h"

// Add a reset line, since Vbusmaster doesn't have one

class   Vbusmasterr : public Vbusmaster {

public:

        int     i_rst;

        virtual ~Vbusmasterr() {}

};

// No particular "parameters" need definition or redefinition here.

class   BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {

public:

        unsigned long   m_tx_busy_count;

        QSPIFLASHSIM    m_flash;

        SDRAMSIM        m_sdram;

        unsigned        m_last_led;

        time_t          m_start_time;

        BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) {

                m_start_time = time(NULL);

        }

        void    reset(void) {

                m_core->i_clk = 1;

                m_core->eval();

        }

        void    tick(void) {

                if ((m_tickcount & ((1<<28)-1))==0) {

                        double  ticks_per_second = m_tickcount;

                        ticks_per_second /= (double)(time(NULL) - m_start_time);

                        printf(" ********   %.6f TICKS PER SECOND\n",

                                ticks_per_second);

                }

                // Set up the bus before any clock tick

                m_core->i_clk = 1;

                m_core->i_spi_miso = m_flash(m_core->o_sf_cs_n,

                                                m_core->o_spi_sck,

                                                m_core->o_spi_mosi)&0x02;

                m_core->i_ram_data = m_sdram(1,

                                m_core->o_ram_cke, m_core->o_ram_cs_n,

                                m_core->o_ram_ras_n, m_core->o_ram_cas_n,

                                m_core->o_ram_we_n, m_core->o_ram_bs,

                                m_core->o_ram_addr, m_core->o_ram_drive_data,

                                m_core->o_ram_data);

                PIPECMDR::tick();

                bool    writeout = false;

                /*

                if (m_core->v__DOT__sdram__DOT__r_pending)

                        writeout = true;

                else if (m_core->v__DOT__sdram__DOT__bank_active[0])

                        writeout = true;

                else if (m_core->v__DOT__sdram__DOT__bank_active[1])

                        writeout = true;

                else if (m_core->v__DOT__sdram__DOT__bank_active[2])

                        writeout = true;

                else if (m_core->v__DOT__sdram__DOT__bank_active[3])

                        writeout = true;

                */

                if (writeout) {

                        printf("%08lx:", m_tickcount);

                        printf("(%d,%d->%d),(%d,%d->%d)|%c[%08x/%08x]@%08x %d%d%c",

                                m_core->v__DOT__wbu_cyc,

                                m_core->v__DOT__dwb_cyc, // was zip_cyc

                                m_core->v__DOT__wb_cyc,

                                //

                                m_core->v__DOT__wbu_stb,

                                // 0, // m_core->v__DOT__dwb_stb, // was zip_stb

                                m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,

                                m_core->v__DOT__wb_stb,

                                //

                                (m_core->v__DOT__wb_we)?'W':'R',

                                m_core->v__DOT__wb_data,

                                        m_core->v__DOT__dwb_idata,

                                m_core->v__DOT__wb_addr,

                                m_core->v__DOT__dwb_ack,

                                m_core->v__DOT__dwb_stall,

                                (m_core->v__DOT__wb_err)?'E':'.');

                        printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",

                                (m_core->v__DOT__sdram_sel)?'!':' ',

                                m_core->o_ram_cs_n, m_core->o_ram_ras_n,

                                m_core->o_ram_cas_n, m_core->o_ram_we_n,

                                m_core->o_ram_bs, m_core->o_ram_data,

                                (m_core->o_ram_drive_data)?'D':'-',

                                m_core->o_ram_addr,

                                        (m_core->o_ram_addr>>10)&1,

                                m_core->i_ram_data,

                                (m_core->o_ram_drive_data)?'-':'V');

                        printf(" SD[%d,%d-%3x%d]",

                                m_core->v__DOT__sdram__DOT__r_state,

                                m_sdram.pwrup(),

                                m_core->v__DOT__sdram__DOT__refresh_clk,

                                m_core->v__DOT__sdram__DOT__need_refresh);

                        printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",

                                m_core->v__DOT__sdram__DOT__bank_active[0],

                                m_core->v__DOT__sdram__DOT__bank_row[0],

                                m_core->v__DOT__sdram__DOT__bank_active[1],

                                m_core->v__DOT__sdram__DOT__bank_row[1],

                                m_core->v__DOT__sdram__DOT__bank_active[2],

                                m_core->v__DOT__sdram__DOT__bank_row[2],

                                m_core->v__DOT__sdram__DOT__bank_active[3],

                                m_core->v__DOT__sdram__DOT__bank_row[3],

                                m_core->v__DOT__sdram__DOT__clocks_til_idle,

                                m_core->v__DOT__sdram__DOT__r_barrell_ack);

                        printf(" %s%s%c[%08x@%06x]",

                                (m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",

                                (m_core->v__DOT__sdram__DOT__r_pending)?"PND":"   ",

                                (m_core->v__DOT__sdram__DOT__r_we)?'W':'R',

                                (m_core->v__DOT__sdram__DOT__r_we)

                                ?(m_core->v__DOT__sdram__DOT__r_data)

                                :(m_core->v__DOT__sdram_data),

                                (m_core->v__DOT__sdram__DOT__r_addr));

                        printf("%s%s%s%s%s%s%s%s%s%s%s%2x",

                                // (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",

                                // (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",

                                // (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",

                                (m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",

                                (m_core->v__DOT__zippy__DOT__cpu_dbg_stall)?"Z":"-",

                                (m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"k":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",

                                (m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-",

                                (m_core->v__DOT__zippy__DOT__cmd_addr));

                        printf("\n");

                }

        }

};

BUSMASTER_TB    *tb;

void    busmaster_kill(int v) {

        tb->kill();

        exit(0);

}

int     main(int argc, char **argv) {

        Verilated::commandArgs(argc, argv);

        tb = new BUSMASTER_TB;

        // signal(SIGINT,  busmaster_kill);

        tb->reset();

        while(1)

                tb->tick();

        exit(0);

}