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dgisselq |
//
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//
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// Filename: pipecmdr.h
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//
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// Project: FPGA testbench utilities.
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//
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// Purpose: This program attaches to a Verilated Verilog IP core.
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// It will not work apart from such a core. Once attached,
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// it connects the simulated core to a controller via a
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// pipe interface designed to act like a UART. Indeed, it
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// is hoped that the final interface would be via UART. Until
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// that point, however, this is just a simple test facility
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// designed to verify that the IP core works prior to such
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// actual hardware implementation.
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//
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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//
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// Copyright: 2015
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//
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//
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#ifndef PIPECMDR_H
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#define PIPECMDR_H
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#include <sys/types.h>
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#include <sys/socket.h>
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#include <poll.h>
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#include <unistd.h>
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#include <arpa/inet.h>
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#include "testb.h"
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#define PIPEBUFLEN 256
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// At 115200 Baud, 8 bits of data, no parity and one stop bit, there will
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// bit ten bits per character and therefore 8681 clocks per transfer
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// 8681 ~= 100 MHz / 115200 (bauds / second) * 10 bauds / character
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//
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// #define UARTLEN 8681 // Minimum ticks per character, 115200 Baud
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//
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// At 4MBaud, each bit takes 25 clocks. 10 bits would thus take 250 clocks
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//
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dgisselq |
// #define UARTLEN 250 // Minimum ticks per character, 4M Baud
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// #define UARTLEN 1000 // Minimum ticks per character, 1M Hz
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// #define UARTLEN 8 // Minimum ticks per character
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#define UARTLEN 4096 //
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dgisselq |
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template <class VA> class PIPECMDR : public TESTB<VA> {
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void setup_listener(const int port) {
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struct sockaddr_in my_addr;
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printf("Listening on port %d\n", port);
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m_skt = socket(AF_INET, SOCK_STREAM, 0);
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if (m_skt < 0) {
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perror("Could not allocate socket: ");
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exit(-1);
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}
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// Set the reuse address option
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{
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int optv = 1, er;
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er = setsockopt(m_skt, SOL_SOCKET, SO_REUSEADDR, &optv, sizeof(optv));
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if (er != 0) {
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perror("SockOpt Err:");
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exit(-1);
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}
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}
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memset(&my_addr, 0, sizeof(struct sockaddr_in)); // clear structure
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my_addr.sin_family = AF_INET;
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my_addr.sin_addr.s_addr = htonl(INADDR_ANY);
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my_addr.sin_port = htons(port);
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if (bind(m_skt, (struct sockaddr *)&my_addr, sizeof(my_addr))!=0) {
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perror("BIND FAILED:");
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exit(-1);
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}
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if (listen(m_skt, 1) != 0) {
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perror("Listen failed:");
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exit(-1);
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}
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}
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public:
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int m_skt, m_con;
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char m_txbuf[PIPEBUFLEN], m_rxbuf[PIPEBUFLEN];
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dgisselq |
int m_ilen, m_rxpos, m_txpos, m_uart_wait, m_tx_busy;
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dgisselq |
bool m_started_flag;
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PIPECMDR(const int port) : TESTB<VA>() {
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m_con = m_skt = -1;
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setup_listener(port);
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m_rxpos = m_txpos = m_ilen = 0;
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m_started_flag = false;
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m_uart_wait = 0; // Flow control into the FPGA
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m_tx_busy = 0; // Flow control out of the FPGA
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}
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virtual void kill(void) {
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// Close any active connection
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if (m_con >= 0) close(m_con);
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if (m_skt >= 0) close(m_skt);
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}
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virtual void tick(void) {
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if (m_con < 0) {
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// Can we accept a connection?
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struct pollfd pb;
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pb.fd = m_skt;
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pb.events = POLLIN;
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poll(&pb, 1, 0);
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if (pb.revents & POLLIN) {
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m_con = accept(m_skt, 0, 0);
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if (m_con < 0)
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perror("Accept failed:");
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}
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}
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TESTB<VA>::m_core->i_rx_stb = 0;
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if (m_uart_wait == 0) {
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if (m_ilen > 0) {
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// Is there a byte in our buffer somewhere?
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TESTB<VA>::m_core->i_rx_stb = 1;
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TESTB<VA>::m_core->i_rx_data = m_rxbuf[m_rxpos++];
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m_ilen--;
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} else if (m_con > 0) {
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// Is there a byte to be read here?
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struct pollfd pb;
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pb.fd = m_con;
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pb.events = POLLIN;
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if (poll(&pb, 1, 0) < 0)
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perror("Polling error:");
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if (pb.revents & POLLIN) {
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if ((m_ilen =recv(m_con, m_rxbuf, sizeof(m_rxbuf), MSG_DONTWAIT)) > 0) {
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m_rxbuf[m_ilen] = '\0';
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if (m_rxbuf[m_ilen-1] == '\n') {
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m_rxbuf[m_ilen-1] = '\0';
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printf("< \'%s\'\n", m_rxbuf);
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m_rxbuf[m_ilen-1] = '\n';
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} else printf("< \'%s\'\n", m_rxbuf);
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TESTB<VA>::m_core->i_rx_stb = 1;
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TESTB<VA>::m_core->i_rx_data = m_rxbuf[0];
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m_rxpos = 1; m_ilen--;
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m_started_flag = true;
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} else if (m_ilen < 0) {
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// An error occurred, close the connection
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dgisselq |
// This could also be the
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// indication of a simple
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// connection close, so we deal
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// with this quietly.
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// perror("Read error: ");
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// fprintf(stderr, "Closing connection\n");
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close(m_con);
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m_con = -1;
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} else { // the connection closed on us
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close(m_con);
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m_con = -1;
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}
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}
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} m_uart_wait = (TESTB<VA>::m_core->i_rx_stb)?UARTLEN:0;
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} else {
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// Still working on transmitting a character
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m_uart_wait = m_uart_wait - 1;
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}
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/*
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if (TESTB<VA>::m_core->i_rx_stb) {
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putchar(TESTB<VA>::m_core->i_rx_data);
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fflush(stdout);
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}
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*/
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TESTB<VA>::tick();
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dgisselq |
bool tx_accepted = false;
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if (m_tx_busy == 0) {
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if ((TESTB<VA>::m_core->o_tx_stb)&&(m_con > 0)) {
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m_txbuf[m_txpos++] = TESTB<VA>::m_core->o_tx_data;
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tx_accepted = true;
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if ((TESTB<VA>::m_core->o_tx_data == '\n')||(m_txpos >= sizeof(m_txbuf))) {
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int snt = 0;
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snt = send(m_con, m_txbuf, m_txpos, 0);
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m_txbuf[m_txpos] = '\0';
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printf("> %s", m_txbuf);
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if (snt < m_txpos) {
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fprintf(stderr, "Only sent %d bytes!\n",
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snt);
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}
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m_txpos = 0;
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}
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}
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} else
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m_tx_busy--;
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if ((TESTB<VA>::m_core->o_tx_stb)&&(TESTB<VA>::m_core->i_tx_busy==0))
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m_tx_busy = UARTLEN;
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TESTB<VA>::m_core->i_tx_busy = (m_tx_busy != 0);
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if (0) {
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if ((m_tx_busy!=0)||(TESTB<VA>::m_core->i_tx_busy)
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||(TESTB<VA>::m_core->o_tx_stb)
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||(tx_accepted))
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printf("%4d %d %d %02x %s\n",
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m_tx_busy,
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TESTB<VA>::m_core->i_tx_busy,
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TESTB<VA>::m_core->o_tx_stb,
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TESTB<VA>::m_core->o_tx_data,
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(tx_accepted)?"READ!":"");
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dgisselq |
}
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dgisselq |
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dgisselq |
/*
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if((TESTB<VA>::m_core->o_wb_cyc)||(TESTB<VA>::m_core->o_wb_stb)){
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printf("BUS: %d,%d,%d %8x %8x\n",
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TESTB<VA>::m_core->o_wb_cyc,
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TESTB<VA>::m_core->o_wb_stb,
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TESTB<VA>::m_core->o_wb_we,
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TESTB<VA>::m_core->o_wb_addr,
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TESTB<VA>::m_core->o_wb_data);
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} else if (m_started_flag) {
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printf("%02x,%c,%d,%d,%02x -> %d,%d,%d, %2x,%2x,%2x\n",
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TESTB<VA>::m_core->i_rx_data,
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(TESTB<VA>::m_core->i_rx_stb)?(TESTB<VA>::m_core->i_rx_data):' ',
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__r_valid,
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__rx_eol,
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__rx_six_bits,
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//
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__o_rq_strobe,
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__o_rq_hold,
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__o_rq_we,
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//
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__state,
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__nreg,
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TESTB<VA>::m_core->v__DOT__decodewb__DOT__szreg);
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}
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*/
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}
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};
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#endif
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