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[/] [xulalx25soc/] [trunk/] [bench/] [cpp/] [qspiflashsim.cpp] - Blame information for rev 112

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1 4 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
//
4
// Filename:    spiflashsim.cpp
5
//
6
// Project:     Wishbone Controlled Quad SPI Flash Controller
7
//
8
// Purpose:     This library simulates the operation of a Quad-SPI commanded
9
//              flash, such as the S25FL032P used on the Basys-3 development
10
//              board by Digilent.  As such, it is defined by 32 Mbits of
11
//              memory (4 Mbyte).
12
//
13
//              This simulator is useful for testing in a Verilator/C++
14
//              environment, where this simulator can be used in place of
15
//              the actual hardware.
16
//
17
// Creator:     Dan Gisselquist
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// You should have received a copy of the GNU General Public License along
35
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
36
// target there if the PDF file isn't present.)  If not, see
37
// <http://www.gnu.org/licenses/> for a copy.
38
//
39
// License:     GPL, v3, as defined and found on www.gnu.org,
40
//              http://www.gnu.org/licenses/gpl.html
41
//
42
//
43
///////////////////////////////////////////////////////////////////////////
44
#include <stdio.h>
45
#include <string.h>
46
#include <assert.h>
47
#include <stdlib.h>
48
 
49
#include "qspiflashsim.h"
50
 
51
#define MEMBYTES        (1<<22)
52
 
53
static  const unsigned  DEVID = 0x0115,
54
        DEVESD = 0x014,
55
        MICROSECONDS = 100,
56
        MILLISECONDS = MICROSECONDS * 1000,
57
        SECONDS = MILLISECONDS * 1000,
58
        tW     =   50 * MICROSECONDS, // write config cycle time
59
        tBE    =   32 * SECONDS,
60
        tDP    =   10 * SECONDS,
61
        tRES   =   30 * SECONDS,
62
// Shall we artificially speed up this process?
63
        tPP    = 12 * MICROSECONDS,
64
        tSE    = 15 * MILLISECONDS;
65
// or keep it at the original speed
66
        // tPP    = 1200 * MICROSECONDS,
67
        // tSE    = 1500 * MILLISECONDS;
68
 
69
QSPIFLASHSIM::QSPIFLASHSIM(void) {
70
        m_mem = new char[MEMBYTES];
71
        m_pmem = new char[256];
72
        m_state = QSPIF_IDLE;
73
        m_last_sck = 1;
74
        m_write_count = 0;
75
        m_ireg = m_oreg = 0;
76
        m_sreg = 0x01c;
77
        m_creg = 0x001; // Iinitial creg on delivery
78
        m_quad_mode = false;
79
        m_mode_byte = 0;
80
 
81
        memset(m_mem, 0x0ff, MEMBYTES);
82
}
83
 
84
void    QSPIFLASHSIM::load(const char *fname) {
85
        FILE    *fp;
86
        int     nr = 0;
87
 
88
        if (NULL != (fp = fopen(fname, "r"))) {
89
                nr = fread(m_mem, sizeof(char), MEMBYTES, fp);
90
                fclose(fp);
91
        } else {
92
                fprintf(stderr, "SPI-FLASH: Could not open %s\n", fname);
93
                perror("O/S Err:");
94
        }
95
 
96
        for(int i=nr; i<MEMBYTES; i++)
97
                m_mem[i] = 0x0ff;
98
}
99
 
100
#define QOREG(A)        m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
101
 
102
int     QSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
103
        // Keep track of a timer to determine when page program and erase
104
        // cycles complete.
105
 
106
        if (m_write_count > 0) {
107
                if (0 == (--m_write_count)) {// When done with erase/page pgm,
108
                        m_sreg &= 0x0fc; // Clear the write in progress bit
109
                        if (m_debug) printf("Write complete, clearing WIP (inside SIM)\n");
110
                }
111
        }
112
 
113
        if (csn) {
114
                m_last_sck = 1;
115
                m_ireg = 0; m_oreg = 0;
116
                m_count= 0;
117
 
118
                if ((QSPIF_PP == m_state)||(QSPIF_QPP == m_state)) {
119
                        // Start a page program
120
                        if (m_debug) printf("QSPI: Page Program write cycle begins\n");
121
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
122
                        if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
123
                        m_write_count = tPP;
124
                        m_state = QSPIF_IDLE;
125
                        m_sreg &= (~QSPIF_WEL_FLAG);
126
                        m_sreg |= (QSPIF_WIP_FLAG);
127
                        for(int i=0; i<256; i++) {
128
                                /*
129
                                if (m_debug) printf("%02x: m_mem[%02x] = %02x &= %02x = %02x\n",
130
                                        i, (m_addr&(~0x0ff))+i,
131
                                        m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
132
                                        m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
133
                                */
134
                                m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
135
                        }
136
                        m_quad_mode = false;
137
                } else if (m_state == QSPIF_SECTOR_ERASE) {
138
                        if (m_debug) printf("Actually Erasing sector, from %08x\n", m_addr);
139
                        m_write_count = tSE;
140
                        m_state = QSPIF_IDLE;
141
                        m_sreg &= (~QSPIF_WEL_FLAG);
142
                        m_sreg |= (QSPIF_WIP_FLAG);
143
                        m_addr &= (-1<<16);
144
                        for(int i=0; i<(1<<16); i++)
145
                                m_mem[m_addr + i] = 0x0ff;
146
                        if (m_debug) printf("Now waiting %d ticks delay\n", m_write_count);
147
                } else if (QSPIF_WRSR == m_state) {
148
                        if (m_debug) printf("Actually writing status register\n");
149
                        m_write_count = tW;
150
                        m_state = QSPIF_IDLE;
151
                        m_sreg &= (~QSPIF_WEL_FLAG);
152
                        m_sreg |= (QSPIF_WIP_FLAG);
153
                } else if (QSPIF_CLSR == m_state) {
154
                        if (m_debug) printf("Actually clearing the status register bits\n");
155
                        m_state = QSPIF_IDLE;
156
                        m_sreg &= 0x09f;
157
                } else if (m_state == QSPIF_BULK_ERASE) {
158
                        m_write_count = tBE;
159
                        m_state = QSPIF_IDLE;
160
                        m_sreg &= (~QSPIF_WEL_FLAG);
161
                        m_sreg |= (QSPIF_WIP_FLAG);
162
                        for(int i=0; i<MEMBYTES; i++)
163
                                m_mem[i] = 0x0ff;
164
                } else if (m_state == QSPIF_DEEP_POWER_DOWN) {
165
                        m_write_count = tDP;
166
                        m_state = QSPIF_IDLE;
167
                } else if (m_state == QSPIF_RELEASE) {
168
                        m_write_count = tRES;
169
                        m_state = QSPIF_IDLE;
170
                } else if (m_state == QSPIF_QUAD_READ_CMD) {
171
                        if ((m_mode_byte & 0x0f0)!=0x0a0)
172
                                m_quad_mode = false;
173
                        else
174
                                m_state = QSPIF_QUAD_READ_IDLE;
175
                } else if (m_state == QSPIF_QUAD_READ) {
176
                        if ((m_mode_byte & 0x0f0)!=0x0a0)
177
                                m_quad_mode = false;
178
                        else
179
                                m_state = QSPIF_QUAD_READ_IDLE;
180
                } else if (m_state == QSPIF_QUAD_READ_IDLE) {
181
                }
182
 
183
                m_oreg = 0x0fe;
184
                return dat;
185
        } else if ((!m_last_sck)||(sck == m_last_sck)) {
186
                // Only change on the falling clock edge
187
                // printf("SFLASH-SKIP, CLK=%d -> %d\n", m_last_sck, sck);
188
                m_last_sck = sck;
189
                if (m_quad_mode)
190
                        return (m_oreg>>8)&0x0f;
191
                else
192
                        // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
193
                        return (m_oreg & 0x0100)?2:0;
194
        }
195
 
196
        // We'll only get here if ...
197
        //      last_sck = 1, and sck = 0, thus transitioning on the
198
        //      negative edge as with everything else in this interface
199
        if (m_quad_mode) {
200
                m_ireg = (m_ireg << 4) | (dat & 0x0f);
201
                m_count+=4;
202
                m_oreg <<= 4;
203
        } else {
204
                m_ireg = (m_ireg << 1) | (dat & 1);
205
                m_count++;
206
                m_oreg <<= 1;
207
        }
208
 
209
 
210
        // printf("PROCESS, COUNT = %d, IREG = %02x\n", m_count, m_ireg);
211
        if (m_state == QSPIF_QUAD_READ_IDLE) {
212
                assert(m_quad_mode);
213
                if (m_count == 24) {
214
                        if (m_debug) printf("QSPI: Entering from Quad-Read Idle to Quad-Read\n");
215
                        if (m_debug) printf("QSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
216
                        m_addr = (m_ireg) & 0x0ffffff;
217
                        assert((m_addr & 0xfc00000)==0);
218
                        m_state = QSPIF_QUAD_READ;
219
                } m_oreg = 0;
220
        } else if (m_count == 8) {
221
                QOREG(0x0a5);
222
                // printf("SFLASH-CMD = %02x\n", m_ireg & 0x0ff);
223
                // Figure out what command we've been given
224
                if (m_debug) printf("SPI FLASH CMD %02x\n", m_ireg&0x0ff);
225
                switch(m_ireg & 0x0ff) {
226
                case 0x01: // Write status register
227
                        if (2 !=(m_sreg & 0x203)) {
228
                                if (m_debug) printf("QSPI: WEL not set, cannot write status reg\n");
229
                                m_state = QSPIF_INVALID;
230
                        } else
231
                                m_state = QSPIF_WRSR;
232
                        break;
233
                case 0x02: // Page program
234
                        if (2 != (m_sreg & 0x203)) {
235
                                if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
236
                                m_state = QSPIF_INVALID;
237
                        } else {
238
                                m_state = QSPIF_PP;
239
                                if (m_debug) printf("PAGE-PROGRAM COMMAND ACCEPTED\n");
240
                        }
241
                        break;
242
                case 0x03: // Read data bytes
243
                        // Our clock won't support this command, so go
244
                        // to an invalid state
245
                        if (m_debug) printf("QSPI INVALID: This sim does not support slow reading\n");
246
                        m_state = QSPIF_INVALID;
247
                        break;
248
                case 0x04: // Write disable
249
                        m_state = QSPIF_IDLE;
250
                        m_sreg &= (~QSPIF_WEL_FLAG);
251
                        break;
252
                case 0x05: // Read status register
253
                        m_state = QSPIF_RDSR;
254
                        if (m_debug) printf("QSPI: READING STATUS REGISTER: %02x\n", m_sreg);
255
                        QOREG(m_sreg);
256
                        break;
257
                case 0x06: // Write enable
258
                        m_state = QSPIF_IDLE;
259
                        m_sreg |= QSPIF_WEL_FLAG;
260
                        if (m_debug) printf("QSPI: WRITE-ENABLE COMMAND ACCEPTED\n");
261
                        break;
262
                case 0x0b: // Here's the read that we support
263
                        if (m_debug) printf("QSPI: FAST-READ (single-bit)\n");
264
                        m_state = QSPIF_FAST_READ;
265
                        break;
266
                case 0x30:
267
                        if (m_debug) printf("QSPI: CLEAR STATUS REGISTER COMMAND\n");
268
                        m_state = QSPIF_CLSR;
269
                        break;
270
                case 0x32: // QUAD Page program, 4 bits at a time
271
                        if (2 != (m_sreg & 0x203)) {
272
                                if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
273
                                m_state = QSPIF_INVALID;
274
                        } else {
275
                                m_state = QSPIF_QPP;
276
                                if (m_debug) printf("QSPI: QUAD-PAGE-PROGRAM COMMAND ACCEPTED\n");
277
                                if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
278
                        }
279
                        break;
280
                case 0x35: // Read configuration register
281
                        m_state = QSPIF_RDCR;
282
                        if (m_debug) printf("QSPI: READING CONFIGURATION REGISTER: %02x\n", m_creg);
283
                        QOREG(m_creg);
284
                        break;
285
                case 0x9f: // Read ID
286
                        m_state = QSPIF_RDID;
287
                        if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>24)&0x0ff);
288
                        QOREG(0xfe);
289
                        break;
290
                case 0xab: // Release from DEEP POWER DOWN
291
                        if (m_sreg & QSPIF_DEEP_POWER_DOWN_FLAG) {
292
                                if (m_debug) printf("QSPI: Release from deep power down\n");
293
                                m_sreg &= (~QSPIF_DEEP_POWER_DOWN_FLAG);
294
                                m_write_count = tRES;
295
                        } m_state = QSPIF_RELEASE;
296
                        break;
297
                case 0xb9: // DEEP POWER DOWN
298
                        if (0 != (m_sreg & 0x01)) {
299
                                if (m_debug) printf("QSPI: Cannot enter DEEP POWER DOWN, in middle of write/erase\n");
300
                                m_state = QSPIF_INVALID;
301
                        } else {
302
                                m_sreg  |= QSPIF_DEEP_POWER_DOWN_FLAG;
303
                                m_state  = QSPIF_IDLE;
304
                        }
305
                        break;
306
                case 0xc7: // Bulk Erase
307
                        if (2 != (m_sreg & 0x203)) {
308
                                if (m_debug) printf("QSPI: WEL not set, cannot erase device\n");
309
                                m_state = QSPIF_INVALID;
310
                        } else
311
                                m_state = QSPIF_BULK_ERASE;
312
                        break;
313
                case 0xd8: // Sector Erase
314
                        if (2 != (m_sreg & 0x203)) {
315
                                if (m_debug) printf("QSPI: WEL not set, cannot erase sector\n");
316
                                m_state = QSPIF_INVALID;
317
                        } else {
318
                                m_state = QSPIF_SECTOR_ERASE;
319
                                if (m_debug) printf("QSPI: SECTOR_ERASE COMMAND\n");
320
                        }
321
                        break;
322
                case 0x0eb: // Here's the (other) read that we support
323
                        // printf("QSPI: QUAD-I/O-READ\n");
324
                        m_state = QSPIF_QUAD_READ_CMD;
325
                        m_quad_mode = true;
326
                        break;
327
                default:
328
                        printf("QSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
329
                        m_state = QSPIF_INVALID;
330
                        assert(0 && "Unrecognized command\n");
331
                        break;
332
                }
333
        } else if ((0 == (m_count&0x07))&&(m_count != 0)) {
334
                QOREG(0);
335
                switch(m_state) {
336
                case QSPIF_IDLE:
337
                        printf("TOO MANY CLOCKS, SPIF in IDLE\n");
338
                        break;
339
                case QSPIF_WRSR:
340
                        if (m_count == 16) {
341
                                m_sreg = (m_sreg & 0x061) | (m_ireg & 0x09c);
342
                                if (m_debug) printf("Request to set sreg to 0x%02x\n",
343
                                        m_ireg&0x0ff);
344
                        } else if (m_count == 24) {
345
                                m_creg = (m_creg & 0x0fd) | (m_ireg & 0x02);
346
                                if (m_debug) printf("Request to set creg to 0x%02x\n",
347
                                        m_ireg&0x0ff);
348
                        } else {
349
                                printf("TOO MANY CLOCKS FOR WRR!!!\n");
350
                                exit(-2);
351
                                m_state = QSPIF_IDLE;
352
                        }
353
                        break;
354
                case QSPIF_CLSR:
355
                        assert(0 && "Too many clocks for CLSR command!!\n");
356
                        break;
357
                case QSPIF_RDID:
358
                        if (m_count == 32) {
359
                                m_addr = m_ireg & 0x0ffffff;
360
                                if (m_debug) printf("READID, ADDR = %08x\n", m_addr);
361
                                QOREG((DEVID>>8));
362
                                if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>8)&0x0ff);
363
                        } else if (m_count > 32) {
364
                                if (((m_count-32)>>3)&1)
365
                                        QOREG((DEVID));
366
                                else
367
                                        QOREG((DEVID>>8));
368
                                if (m_debug) printf("QSPI: READING ID, %02x -- DONE\n", 0x00);
369
                        }
370
                        // m_oreg = (DEVID >> (2-(m_count>>3)-1)) & 0x0ff;
371
                        break;
372
                case QSPIF_RDSR:
373
                        // printf("Read SREG = %02x, wait = %08x\n", m_sreg,
374
                                // m_write_count);
375
                        QOREG(m_sreg);
376
                        break;
377
                case QSPIF_RDCR:
378
                        if (m_debug) printf("Read CREG = %02x\n", m_creg);
379
                        QOREG(m_creg);
380
                        break;
381
                case QSPIF_FAST_READ:
382
                        if (m_count == 32) {
383
                                m_addr = m_ireg & 0x0ffffff;
384
                                if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
385
                                QOREG(0x0c3);
386
                                assert((m_addr & 0xfc00000)==0);
387
                        } else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
388
                                if (m_count == 40)
389
                                        printf("DUMMY BYTE COMPLETE ...\n");
390
                                QOREG(m_mem[m_addr++]);
391
                                // if (m_debug) printf("SPIF[%08x] = %02x\n", m_addr-1, m_oreg);
392
                        } else m_oreg = 0;
393
                        break;
394
                case QSPIF_QUAD_READ_CMD:
395
                        // The command to go into quad read mode took 8 bits
396
                        // that changes the timings, else we'd use quad_Read
397
                        // below
398
                        if (m_count == 32) {
399
                                m_addr = m_ireg & 0x0ffffff;
400
                                // printf("FAST READ, ADDR = %08x\n", m_addr);
401
                                // printf("QSPI: QUAD READ, ADDR = %06x\n", m_addr);
402
                                assert((m_addr & 0xfc00000)==0);
403
                        } else if (m_count == 32+24) {
404
                                m_mode_byte = (m_ireg>>16) & 0x0ff;
405
                                // printf("QSPI: MODE BYTE = %02x\n", m_mode_byte);
406
                        } else if ((m_count > 32+24)&&(0 == (m_sreg&0x01))) {
407
                                QOREG(m_mem[m_addr++]);
408
                                // printf("QSPIF[%08x]/QR = %02x\n",
409
                                        // m_addr-1, m_oreg);
410
                        } else m_oreg = 0;
411
                        break;
412
                case QSPIF_QUAD_READ:
413
                        if (m_count == 32) {
414
                                m_mode_byte = (m_ireg & 0x0ff);
415
                                // printf("QSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
416
                        } else if ((m_count >= 32+16)&&(0 == (m_sreg&0x01))) {
417
                                QOREG(m_mem[m_addr++]);
418
                                // printf("QSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
419
                        } else m_oreg = 0;
420
                        break;
421
                case QSPIF_PP:
422
                        if (m_count == 32) {
423
                                m_addr = m_ireg & 0x0ffffff;
424
                                if (m_debug) printf("QSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
425
                                assert((m_addr & 0xfc00000)==0);
426
                                // m_page = m_addr >> 8;
427
                                for(int i=0; i<256; i++)
428
                                        m_pmem[i] = 0x0ff;
429
                        } else if (m_count >= 40) {
430
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
431
                                // printf("QSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
432
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
433
                        } break;
434
                case QSPIF_QPP:
435
                        if (m_count == 32) {
436
                                m_addr = m_ireg & 0x0ffffff;
437
                                m_quad_mode = true;
438
                                if (m_debug) printf("QSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
439
                                assert((m_addr & 0xfc00000)==0);
440
                                // m_page = m_addr >> 8;
441
                                for(int i=0; i<256; i++)
442
                                        m_pmem[i] = 0x0ff;
443
                        } else if (m_count >= 40) {
444
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
445
                                // printf("QSPI/QR: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
446
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
447
                        } break;
448
                case QSPIF_SECTOR_ERASE:
449
                        if (m_count == 32) {
450
                                m_addr = m_ireg & 0x0ffc000;
451
                                if (m_debug) printf("SECTOR_ERASE ADDRESS = %08x\n", m_addr);
452
                                assert((m_addr & 0xfc00000)==0);
453
                        } break;
454
                case QSPIF_RELEASE:
455
                        if (m_count >= 32) {
456
                                QOREG(DEVESD);
457
                        } break;
458
                default:
459
                        break;
460
                }
461
        } // else printf("SFLASH->count = %d\n", m_count);
462
 
463
        m_last_sck = sck;
464
        if (m_quad_mode)
465
                return (m_oreg>>8)&0x0f;
466
        else
467
                // return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
468
                return (m_oreg & 0x0100)?2:0;
469
}
470
 

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