OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [bench/] [cpp/] [qspiflashsim.h] - Blame information for rev 105

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    spiflashsim.h
4
//
5
// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
7
// Purpose:     This library simulates the operation of a Quad-SPI commanded
8
//              flash, such as the S25FL032P used on the Basys-3 development
9
//              board by Digilent.  As such, it is defined by 32 Mbits of
10
//              memory (4 Mbyte).
11
//
12
// Creator:     Dan Gisselquist
13
//              Gisselquist Technology, LLC
14
//
15
///////////////////////////////////////////////////////////////////////////
16
//
17
// Copyright (C) 2015, Gisselquist Technology, LLC
18
//
19
// This program is free software (firmware): you can redistribute it and/or
20
// modify it under the terms of  the GNU General Public License as published
21
// by the Free Software Foundation, either version 3 of the License, or (at
22
// your option) any later version.
23
//
24
// This program is distributed in the hope that it will be useful, but WITHOUT
25
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
26
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
27
// for more details.
28
//
29
// You should have received a copy of the GNU General Public License along
30
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
31
// target there if the PDF file isn't present.)  If not, see
32
// <http://www.gnu.org/licenses/> for a copy.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////
39
#ifndef QSPIFLASHSIM_H
40
#define QSPIFLASHSIM_H
41
 
42
#define QSPIF_WIP_FLAG                  0x0001
43
#define QSPIF_WEL_FLAG                  0x0002
44
#define QSPIF_DEEP_POWER_DOWN_FLAG      0x0200
45
class   QSPIFLASHSIM {
46
        typedef enum {
47
                QSPIF_IDLE,
48
                QSPIF_QUAD_READ_IDLE,
49
                QSPIF_RDSR,
50
                QSPIF_RDCR,
51
                QSPIF_WRSR,
52
                QSPIF_CLSR,
53
                QSPIF_RDID,
54
                QSPIF_RELEASE,
55
                QSPIF_FAST_READ,
56
                QSPIF_QUAD_READ_CMD,
57
                QSPIF_QUAD_READ,
58
                QSPIF_SECTOR_ERASE,
59
                QSPIF_PP,
60
                QSPIF_QPP,
61
                QSPIF_BULK_ERASE,
62
                QSPIF_DEEP_POWER_DOWN,
63
                QSPIF_INVALID
64
        } QSPIF_STATE;
65
 
66
        QSPIF_STATE     m_state;
67
        char            *m_mem, *m_pmem;
68
        int             m_last_sck;
69
        unsigned        m_write_count, m_ireg, m_oreg, m_sreg, m_addr,
70
                        m_count, m_config, m_mode_byte, m_creg;
71
        bool            m_quad_mode, m_debug;
72
 
73
public:
74
        QSPIFLASHSIM(void);
75
        void    load(const char *fname);
76
        void    debug(const bool dbg) { m_debug = dbg; }
77
        bool    debug(void) const { return m_debug; }
78
        int     operator()(const int csn, const int sck, const int dat);
79
};
80
 
81
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.